Fabrication method for a thin film semiconductor device, the thin film semiconductor device itself, liquid crystal display, and electronic device

ABSTRACT

In order to fabricate a high performance thin film semiconductor device using a low temperature process in which it is possible to use low price glass substrates, a thin film semiconductor device has been fabricated by forming a silicon film at less than 450° C., and, after crystallization, keeping the maximum processing temperature at or below 350° C.  
     In applying the present invention to the fabrication of an active matrix liquid crystal display, it is possible to both easily and reliably fabricate a large, high-quality liquid crystal display. Additionally, in applying the present invention to the fabrication of other electronic circuits as well, it is possible to both easily and reliably fabricate high-quality electronic circuits.

FIELD OF TECHNOLOGY

[0001] The present invention is related to the fabrication method for athin film semiconductor device, the thin film semiconductor deviceitself, liquid crystal displays, and electronic devices applicable toactive matrix liquid crystal displays and the like.

BACKGROUND TECHNOLOGY

[0002] In recent years, along with increases in screen size andimprovements in resolution, the driving-methods for liquid crystaldisplays (LCDs) are moving from simple matrix methods to active matrixmethods; and the displays are becoming capable of displaying largeamounts of information. LCDs with more than several hundreds ofthousands pixels are possible with active matrix methods which place aswitching transistor at each pixel. Transparent insulating substratessuch as fused quartz and glass which allow the fabrication oftransparent displays are used as substrates for all types of LCDs.Although ordinarily semiconductor layers such as amorphous silicon orpolycrystalline silicon are used as the active layer in thin filmtransistors (TFTs), the use of polycrystalline silicon which has higheroperating speeds is advantageous for the case of producing monolithicdisplays which include integrated driving circuits. When polycrystallinesilicon is used as the active layer, fused quartz is used as thesubstrate; and a so-called “high temperature” process in which themaximum processing temperature exceeds 1000° C. is used to fabricate theTFTs. On the other hand, for the case of an amorphous silicon activelayer, a common glass substrate can be used. For increases in LCDdisplay size while maintaining low costs, such use of low-cost commonglass substrates is indispensable. Such amorphous silicon layers,however, have such problems as electrical characteristics far inferiorto those of polysilicon layers and slow operating speed. Since the hightemperature process polysilicon TFTs use quartz substrates, however,there are problems with increasing display size and decreasing costs.Consequently, there is a strong need for technology which can fabricatea thin film semiconductor device employing a semiconductor layer such aspolycrystalline silicon as the active layer upon a common glasssubstrate. But, when using large substrates which are well-suited tomass production, there is a severe restriction in that the substratesmust be kept below a maximum processing temperature of about 570° C. inorder to avoid deformation of the substrates. In other words, technologywhich can produce, under such restrictions, the active layer of thinfilm transistors capable of controlling a liquid crystal display and ofthin film transistors which can operate driving circuits at high speedis desired. These devices are currently known as the present lowtemperature poly-Si TFTs.

[0003] Previous low temperature poly-Si TFTs are shown on p. 387 of theSID (Society for Information Display) '93 Digest (1993). According tothis description, 50 nm of amorphous silicon (a-Si) is first depositedat 500° C. by LPCVD using monosilane (SiH₄) as the source gas and thenconverted from a-Si to poly-Si by laser irradiation. After patterning ofthe poly-Si layer, a gate insulator layer of SiO₂ is deposited byECR-PECVD at a substrate temperature of 100° C. Following formation ofthe tantalum (Ta) gate electrode on top of the gate insulator layer,self-aligned transistor source and drain regions are formed in thesilicon layer by ion implantation of donor or acceptor impurities whileusing the gate electrode as a mask. This ion implantation, known as “iondoping”, is accomplished by a non-mass separating ion implanter.Hydrogen-diluted phosphine (PH₃), diborane (B₂H₆) or similar gas is usedas a source gas for ion doping. Activation of the impurities is carriedout at 300° C. Following deposition of an interlevel insulator layer,electrodes and interconnects such as indium tin oxide (ITO) and aluminum(Al) are deposited to complete the thin film semiconductor device.

[0004] As described below, however, there are several inherent problemswith poly-Si TFTs fabricated by the existing technology in the lowtemperature process which act as impediments to the adoption of thistechnology into mass production.

[0005] 1. The high processing temperature of 550° C. prevents the use oflow-priced glass leading to a steep rise in product prices.Additionally, the degree of warp of the glass substrates as a result oftheir own weight increases as substrate size increases, and increases inliquid crystal display (LCD) sizes are not possible.

[0006] 2. The appropriate irradiation conditions necessary to obtainuniform laser irradiation over the entire substrate are severe and fallwithin a narrow range. As a result, the crystallization of the film canvary from uniform to non-uniform from lot to lot and reliable productionis not possible.

[0007] 3. During the ion doping or subsequent low temperature activationat 300-350° C. of the source and drain regions which are self-alignedwith respect to the gate electrode, the problem of unsuccessfulactivation occasionally occurs. In other words, the resistance of thesource and drain regions is several gigaohms. Especially when producingTFTs with lightly doped drains (LDD), this problem is serious and is acause of significant decreases in production yield.

[0008] 4. Although only SiO₂ formed by ECR-PECVD yields suitabletransistor properties in low temperature process poly-Si TFTs, it isdifficult to increase the size of the ECR source in the ECR-PECVDequipment thereby making ECR-PECVD unsuitable for large LCD panels.Furthermore, the throughput is extremely poor. Consequently, ECR-PECVDreactors are not suitable as mass production-compatible, practical gateoxide film deposition equipment applicable to the manufacture of largesize displays.

[0009] 5. Use of means such as laser irradiation for meltcrystallization of semiconductor films like silicon results in partialagglomeration which can lead to large variations in the electricalproperties of the semiconductor layer, roughness of the semiconductorlayer, and decreases in the gate-source or gate-drain electricalbreakdown strength.

[0010] 6. When low cost, conventional glass substrates were used, theunderlevel protection layer necessary to effectively prevent penetrationof impurities from the glass into the semiconductor layer was not theunderlevel protection layer of the semiconductor devices which showedthe optimum electrical properties. In other words, making the underlevelprotection layer thicker to prevent impurity penetration leads to thedeterioration of the electrical properties of the semiconductor devicefrom stress generated by the underlayer or generates cracks in thesemiconductor device.

[0011] 7. When plasma enhanced chemical vapor deposition (PECVD) is usedto produce the semiconductor films, elements such as fluorine (F) andcarbon (C), constitutive elements of vapors used in cleaning thedeposition chamber which may remain after cleaning, may be incorporatedas impurities into the films. The result is that the amount ofimpurities incorporated into the substrates varies, and it is notpossible to reliably produce excellent thin film semiconductor devices.

[0012] 8. As the deposition temperature for semiconductor films in lowpressure chemical vapor deposition (LPVCD) decreases, compatibilitybetween uniformity within a substrate and the deposition rate isdifficult. In other words, because the deposition rate decreases whenthe deposition temperature is lowered, the increase in pressurenecessary to compensate for this behavior results in significantworsening of the uniformity over a single substrate. This tendencybecomes noticeably more pronounced as the substrate size becomes largerand is a major obstacle to the mass production of large LCDs.

[0013] 9. There are three types of non-uniformity of the electricalcharacteristics of thin film semiconductor devices. In addition tovariations within a single substrate, there are also variations fromsubstrate to substrate in a single lot as well as variations betweendifferent lots. In the thin film semiconductor devices and thefabrication procedures of the existing technology, it is not possible tocontrol these three types of non-uniformity. In particular, there hasbeen almost no thought given to the variation in properties seen fromlot to lot.

[0014] 10. In the fabrication of semiconductor thin films by PECVD, theadhesion between the semiconductor layer and the protective underlayeris poor; and numerous crater-shaped holes are generated in thesemiconductor layer which can lead to delamination of the film in theworst case.

[0015] The present invention aims to solve the problems noted above withthe purpose of providing a means for reliably producing good thin filmsemiconductor devices through a realistically convenient method using aprocessing temperature which will allow the use of common large glasssubstrates.

DESCRIPTION OF THE INVENTION

[0016] The fundamental principles and operation of the present inventionwill be explained with reference to the drawings.

[0017] FIGS. 1(a) through (d) are cross-sectional schematicrepresentations of the fabrication process for thin film semiconductordevices constituting an MIS field effect transistor. After giving anoutline of the low temperature poly-Si TFT fabrication process usingthese figures, the details of the present invention will be explainedfor each processing step.

[0018] (1, Outline of the Fabrication Procedure of a Thin FilmSemiconductor Device of the Present Invention)

[0019] In the present invention, a conventional non-alkaline glass isused as an example for substrate 101. First, an insulating underlevelprotection layer 102 is formed on top of substrate 101 by a techniquesuch as atmospheric pressure chemical vapor deposition (APCVD), PECVD,or sputtering. Next, a semiconductor layer such as intrinsic silicon,which will later become the active layer of the semiconductor device, isdeposited. The semiconductor layer can be formed by chemical vapordeposition (CVD) such as LPCVD, PECVD, or APCVD or by physical vapordeposition (PVD) such as sputtering or evaporation. Crystallization ofthe semiconductor layer so fabricated is achieved by short-timeirradiation using electromagnetic energy or optical energy such as fromlaser light. When the originally deposited semiconductor layer isamorphous or a mixture of amorphous and microcrystalline material, thisprocess is known as crystallization. On the other hand, if theoriginally deposited semiconductor layer is polycrystalline, the processis known as recrystallization. In this description of the presentinvention, both are simply referred to as “crystallization” unless it isnecessary to make a distinction. If the intensity of the energy fromlaser light or other source is high, the semiconductor layer willcrystallize by initially melting and then solidifying upon cooling. Thisis known as melt crystallization in the present invention. Conversely,crystallization in which the semiconductor layer does not melt butproceeds in the solid state is known as solid phase crystallization(SPC). Solid phase crystallization can be divided mainly into threetypes: furnace-SPC in which crystallization occurs at temperatures from550° C. to 650° C. for times ranging from a few hours to several tens ofhours, rapid thermal annealing (RTA) in which crystallization occurs ina very short time frame ranging from less than one second up to aboutone minute at temperatures of 700 to 1000° C., and very short time-SPC(VST-SPC) using low intensity energy such as from a laser. Although allthree types are suitable for use in the present invention, meltcrystallization, RTA and VST-SPC are particularly appropriate whenconsidered in light of processing which allows high productivity forlarge substrates. The reason for this is not only that thesecrystallization methods use extremely short irradiation periods but alsothat the whole substrate is not heated during crystallization of thesemiconductor layer since the irradiated area is localized with respectto the entire substrate area; and, therefore, no heat-induceddeformation or cracking of the substrate occurs. Followingcrystallization, the semiconductor layer is patterned; and then theactive semiconductor layer 103 is produced. See FIG. 1(a).

[0020] After formation of the semiconductor layer, the gate insulatorlayer 104 is formed by a method such as CVD or PVD. Several methods canbe considered for the fabrication of insulating films, but a fabricationtemperature of 350° C. or less is desirable. This is essential to avoidthermal degradation of the MOS interface and the insulating film. Thisis applicable to subsequent steps in the fabrication process as well.Processing temperatures following fabrication of the gate insulatorlayer must be kept at or below 350° C. Doing so allows high performancesemiconductor devices to be produced both easily and reliably.

[0021] Next, a thin film which will become the gate electrode 105 isdeposited by a method such as PVD or CVD. Since the same material isusually used for both the gate electrode and the gate interconnects andboth are fabricated in the same step, it is desirable to use a materialwhich has low electrical resistance and is stable with respect tothermal processing around 350° C. After patterning of the thin film forthe gate electrode, ion incorporation 106 into the semiconductor layeris employed to form the source and drain regions 107 and the channelregion 108. See FIG. 1(c). During this process, the gate electrode actsas a mask for ion implantation so that the channel is formed onlyunderneath the gate in a self-aligned structure. For impurity ionincorporation, both ion doping, in which non-mass separation equipmentis used and hydrogenated impurity species as well as hydrogen areincorporated into the film, and ion implantation, in whichmass-separation ion implanters are used and only the desired impuritiesthemselves are incorporated into the film, are applicable. Source gasesfor ion doping use hydrogenated species of the impurity ions such asphosphine (PH₃) and diborane (B₂H₆) which are diluted in hydrogen toconcentrations of 0.1% to 10%. In the case of ion implantation, hydrogenions (protons or molecular hydrogen ions) are implanted following theimplantation of the desired impurity elements by themselves. In order tomaintain a stable MOS interface and gate insulator layer, thetemperature must be kept at or below 350° C. for both ion doping and ionimplantation. In order to always reliably carry out the impurityactivation at a low temperature of 350° C. or less, it is desirable tokeep the substrate temperature above 200° C. during implantation. On theother hand, to ensure a low temperature activation of impurity ionsimplanted in the channel to control the transistor threshold voltage orimpurity ions implanted in lightly doped regions such as those used toform an LDD structure, it is necessary to keep the substrate temperatureat or above 250° C. during ion implantation. The result is thatamorphization of the ion implanted region can be avoided by performingthe ion implantation at a such a high substrate temperature sincerecrystallization occurs simultaneously with damage to the semiconductorlayer. In other words, the ion implanted region remains crystallinefollowing implantation, and the subsequent activation of the implantedions can still be achieved using a low activation annealing temperatureof less than about 350° C. When fabricating a CMOS TFT, the NMOS or PMOSregion is alternately covered by a suitable mask material such aspolyimide resin, and ion implantation. is performed using the procedureabove. If the substrate temperature is kept below approximately 300° C.during ion implantation, it is possible to use a cheap, easily preservedconventional photoresist as an ion implantation mask instead of thepolyimide.

[0022] Next, the interlevel insulator film 109 is formed by either CVDor PVD. Following ion implantation and interlevel insulator filmformation, ion activation and interlevel insulator film densificationare carried out by thermal annealing in a suitable thermal environmentat temperatures less than about 350° C. for a time ranging from severaltens of minutes to a few hours. It is desirable for this annealingtemperature to be greater than approximately 250° C. to ensureactivation of the implanted ions. Additionally, for effectivedensification of the interlevel insulator film, a temperature of 300° C.or higher is preferred. The film quality of the gate insulator layer andthe interlevel insulator layer are normally different. Accordingly,during the opening of contact holes in the two insulator films followinginterlevel insulator film formation, it is common for the etching ratesin the two films to be different. Under such conditions, an inversetaper in which the bottom of the contact hole is wider than the top orthe formation of a canopy can result. During electrode formation, theseundesirable structures can be causes of poor contact between theelectrode and underlying layers in the device leading to so-called“contact failure.” The generation of contact failure can be minimized byeffective densification of the interlevel insulator film. Followingformation of the interlevel insulator layer, contact holes are openedabove the source and drain regions; and source and drain electrodes 110and interconnects are formed by PVD or CVD to complete the fabricationof the thin film semiconductor device. See FIG. 1(d).

[0023] (2, Detailed Explanations of the Individual Steps in theFabrication Process of the Thin Film Semiconductor Device of the PresentInvention)

[0024] (2-1, Substrates and Underlevel Protection Layers Suitable forthe Present Invention)

[0025] First, substrates and underlevel protection layers suitable forthe present invention will be explained. For the present invention,substrates including conductive materials such as metals; ceramicmaterials such as silicon carbide (SiC), alumina (Al₂O₃), and aluminumnitride (AlN); transparent insulating materials such as fused quartz andglass; semiconductor substrates such as silicon wafers or processed LSI;and crystalline insulators such as sapphire (trigonal Al₂O₃) can beused. Low priced conventional glass substrates which can be used includeCorning Japan's 7059 and 1737 glasses, Nippon Electric Glass Co., Ltd.'sOA-2 glass, and NH Techno Glass's NA35. The type of substrate isimmaterial for the semiconductor film; and, as long as least part of thesubstrate surface is composed of an insulating material, thesemiconductor layer can be deposited on top of the insulating material.This insulating material is known as the underlevel protection layer inthe present invention disclosure. For example, if a fused quartzsubstrate is used as a substrate, it is acceptable to deposit asemiconductor film directly on top of the fused quartz substrate sincethe substrate itself is insulating. Or, it is acceptable to deposit thesemiconductor film on top of an underlevel protection layer such assilicon oxide (SiO_(x): 0<×≦2) or silicon nitride (Si₃N_(x): 0<×≦4)which has been formed on top of the quartz substrate. When using anordinary glass substrate, it is possible to deposit the semiconductorfilm directly on top of the insulating glass, but it is desirable todeposit the semiconductor film after the formation of an insulatingunderlevel protection layer such as silicon oxide or silicon nitride toavoid penetration of mobile ions like sodium (Na), which are containedin the glass substrate, into the semiconductor film. By so doing, theoperational properties of the semiconductor device do not vary underoperation over a long time period or under high voltages, and thestability is increased. In the present invention, this stability iscalled transistor reliability. With the exception of using crystallineinsulating materials such as sapphire as substrates, it is desirable todeposit the semiconductor film on top of an underlevel protection layer.When using any type of ceramics as a substrate, the underlevelprotection layer serves to prevent sintering aids added to the ceramicsfrom diffusing into the semiconductor regions. In the case of metallicsubstrates, the use of an underlevel protection layer is essential tomaintain the insulating properties. Further, with semiconductorsubstrates or LSI elements, interlevel insulator films betweentransistors or between interconnects serve the role of underlevelprotection layers. The substrate size and shape adds no additionalrestrictions as long as the substrates do not shrink or distort in thethermal environment during processing. Substrates can be anywhere on theorder of 3 inch diameter (76.2 mm) disks to 560 mm ×720 mm rectangularplates.

[0026] After the substrate has been cleaned in deionized water, anunderlevel protection layer of an oxide such as silicon oxide, aluminumoxide, or tantalum oxide; or a nitride such as silicon nitride is formedon the substrate by CVD methods such as APCVD, LPCVD, or PECVD; or byPVD methods. Oxides and nitrides can be formed by initially forming ametallic layer such as silicon, aluminum, or tantalum on the substrateand then using a thermochemical or electrochemical reaction. Forexample, it is possible to form an approximately 200 nm thermal tantalumoxide film by first sputtering about 100 nm of tantalum and then heatingin an oxidizing atmosphere at about 450° C. to achieve thermaloxidation. Using APCVD, it is possible to deposit a silicon oxide filmusing monosilane (SiH₄) and oxygen as source gases at a substratetemperature of about 250 to 450° C. PECVD and sputtering can formunderlevel protection layers using substrate temperatures between roomtemperature and approximately 400° C.

[0027] In the present invention, because the semiconductor layer formedon top of the underlevel protection layer functions as the active layerfor the transistor and this semiconductor layer is formed bycrystallization, the properties of the underlevel protection layer havea strong influence on the quality of the semiconductor layer. First, itis desirable to have the center line mean surface roughness of theunderlevel protection layer be 3.0 nm or less. When a semiconductor filmsuch as silicon is deposited by CVD on top of an underlevel protectionlayer, the very first stage in film formation is the generation of manynuclei on top of the substrate. While these nuclei gradually grow, newnuclei form at sites on the underlevel protection layer which are notyet populated by nuclei. All of these nuclei grow, impinge on eachother, and eventually link to form a film. Regardless of whether thefilm is amorphous or crystalline, all deposited films, having theirorigin in such growth mechanisms, are constructed from regionscorresponding to nuclei in the early stages of growth. Consequently, ifthe nuclei density is low, the regions constituting the film will becomelarge. If the regions in the semiconductor film prior to crystallizationare large, the grains constituting the crystallized film will also belarge. When the grains in the semiconductor film are large, theelectrical properties, such as mobility, of the semiconductor devicehaving an active layer comprised of these grains improve. According tothe experiments of the inventor, it has become clear that the nucleidensity can be kept low if the center line mean surface roughness isabout 3.0 nm or less with the result being the ability to fabricate highperformance semiconductor devices. The reason for this seems to be thatthe irregularity in the surface of the underlevel protection layer isone factor in nucleation, and the nucleation density increases as thesurface irregularity becomes more pronounced. Further, it is desirableto have the center line mean surface roughness of the underlevelprotection layer be about 1.5 nm or less when the semiconductor layer ismelt crystallized. If the surface is this smooth, the meltedsemiconductor material such as silicon spreads readily over theunderlevel protection layer. Because of this, large diameter grains cangrow easily; and the properties of the thin film semiconductor deviceare improved dramatically. At the same time, local agglomeration of themolten material during solidification of the melted semiconductormaterial does not occur; and the uniformity within the molten regionincreases. The LSI scaling law applies to thin film semiconductordevices as well; and it appears that the miniaturization of elementswill continue in step with future integration. As transistor sizescontinue to shrink from the 1 μm order to submicron order, how to avoidlocal agglomeration will be an important issue. When fabricating thesemiconductor layer by melt crystallization, the center line meansurface roughness of the underlevel protection layer is ideally 1.0 nmor less. By meeting this criterion, it is possible to produce uniformfilms, without local agglomeration, from semiconductor films withlarge-diameter grains.

[0028] Another role of the underlevel protection layer is to prevent thediffusion of impurity elements from the substrate. To do so, it iseffective to combine at least two or more different types of films in alayered structure to act as the underlevel protection layer. Forexample, a layered structure comprising, from the substrate, a tantalumoxide film, a silicon nitride film, and a silicon oxide film can beused. There are various types of impurity elements in normal substrates,and these elements have different diffusion coefficients in thedifferent insulators mentioned above. It is easily possible to have acertain impurity element which diffuses slowly through one of the layerscomprising the underlevel protection layer but diffuses quickly throughanother layer. There are various impurity elements contained withinsubstrates; and, since there is a fixed underlevel protection layerthickness as will be explained later, underlevel protection layersformed by layering of different layers are more effective in preventingthe diffusion of impurities than single layers. Many different materialscan be considered for the underlevel protection layer; but, from theviewpoint of ease of fabrication by processes such as CVD, compositelayers of silicon nitride and silicon oxide are the most appropriate. Insuch two-layer composite or multilayer composite underlevel protectionlayers, it is desirable to have the upper most layer be of siliconoxide. This is because the interface states which are inevitablygenerated between the underlevel protection layer and the semiconductorlayer are minimized using silicon oxide. Especially for thinsemiconductor films less than a few hundred nm in which the depletionlayer formed under the transistor operating conditions can consume theentire semiconductor layer thickness, it is essential to suppress suchinterface states. In the present invention, the optimum semiconductorfilm thickness for the thin film semiconductor device varies slightlydepending on the fabrication process but is less than approximately 150nm. Nevertheless, because the quality of the semiconductor film is high,there are few grain boundary trapping states-and few intragranulardefects. On account of this, the depletion layer extends completelythrough the semiconductor film when the transistor is in operation. Ifthere are many interface states generated at the interface between theunderlevel protection layer and the semiconductor layer, the spread ofthe depletion layer during channel formation is delayed, leading to ahigh threshold voltage since the interface states effectively act thesame as donor and acceptor ions. In other words, these interface statescan become one factor in the degradation of transistor properties. Theeffect of the surface of the underlevel protection layer on transistorproperties appears when the semiconductor layer is less thanapproximately 150 nm thick, and when the effective doping concentrationin the channel layer {[(acceptor ion concentration)−(donor ionconcentration)+(concentration of trapping states and crystal defectsacting as acceptor ions)] for the case of NMOS; [(donor ionconcentration)−(acceptor ion concentration)+(concentration of trappingstates and crystal defects acting as donor ions)] for the case of PMOS}is less than about 1×10¹⁶ cm⁻³, or when the threshold voltage of thethin film semiconductor device is less than approximately 4.5 V. Torestore the properties of transistors satisfying these conditions, it isimperative to control the surface of the underlevel insulator layer; andone way to do this is to use silicon oxide as the top layer in amutilayer underlevel protection layer composite.

[0029] It is necessary to have a sufficiently thick underlevelprotection layer to prevent the diffusion of impurity ions from thesubstrate into the semiconductor device, and this thickness is on theorder of 100 nm as a minimum. Considering variations from lot to lot orfrom wafer to wafer within a single lot, it is better to have athickness greater than 200 nm; and, if the thickness is 300 nm, the filmcan function sufficiently as a protection layer. When the underlevelprotection layer also serves as an interlevel insulator layer between ICelements or the interconnects connecting such elements, a thickness offrom 400 to 600 nm is common. Since too thick of an insulating layer isa cause of stress which can lead to cracking, however, a maximumthickness of about 2 μm is preferable. Consideration of throughput,however, reduces the maximum thickness to 1 μm. For the case mentionedpreviously of a composite interlevel protection layer comprising abottom layer of silicon nitride and a top layer of silicon oxide, thesame relations hold; and it is necessary to have a total thickness of100 nm with each layer 50 nm thick. In the thin film semiconductordevice of the present invention, the gate insulator layer is formed byCVD or PVD at a temperature below about 350° C. To obtain a clean MOSinterface for this process, the native oxide layer on the semiconductorlayer surface is removed immediately prior to gate oxide film formation.This native oxide removal step does not remove only the native oxide onthe surface of the semiconductor layer, but also unfortunately removespart of the exposed underlevel silicon oxide layer surface not coveredby the semiconductor layer. Even after the native oxide removal step,there must be 100 nm or more of the underlevel protection layer siliconoxide for the layer to function properly. In other words, the minimumthickness of the silicon oxide layer is about 100 nm, and the minimumthickness of the silicon nitride is about 50 nm. For a thickness of lessthan 50 nm, the film islands do not link to form a complete film leavinggaps sporadically throughout the film. Since an underlevel protectionlayer loses its ability to prevent diffusive impurity penetration, it isnecessary to have a minimum film thickness of 50 nm even when severalfilms are used. As mentioned previously, the upper limit on thethickness of silicon nitride and silicon oxide films is 2 μm. Because anunderlevel protection layer film thickness of 300 nm is sufficient andthicker films actually are stressed leading to cracking or degradationof transistor properties, the ideal upper limit is approximately 500 nm.When several layers are combined in a composite layered structure, thestress conditions from each film are different; and if the thicknessesof all films are kept below about 500 nm, there should be no problems.

[0030] In general, silicon oxide films deposited by CVD or PVD attemperatures less than about 350° C. have high internal stress. It iscommon to relieve a portion of such stress by high temperature thermalannealing following deposition. In the low temperature process of thepresent invention, however, the maximum processing temperature must bekept below about 350° C. following gate insulator formation. Since it isdifficult to relieve stress in a silicon oxide film subjected to onlysuch a low temperature anneal, silicon oxide films thicker than about 2μm can lead to cracks in the substrate. Additionally, along withincreases in substrate size such as those greater than 300 mm ×300 mm,it becomes easier for stresses to accumulate and induce cracking in thesubstrate. The conditions are the same regardless of whether the siliconoxide film is a single layer or a composite structure, and cracks aregenerated if the total silicon oxide film thickness is 2 μm or more. Inthe thin film semiconductor device of the present invention, anunderlevel protection layer of an insulating material is deposited on aportion of the substrate; and this is followed by fabrication of a fieldeffect transistor, comprising a semiconductor layer, gate insulator, andgate electrode, on top of the underlevel protection layer. This is thenfollowed by formation of an interlevel insulator layer between theinterconnects of the field effect transistor to achieve electricalisolation. In addition to at least the upper-most layer of theunderlevel protection layer being of silicon oxide, so is the MOSinterface part of the gate insulator; and it is normal to also usesilicon oxide in at least a portion of the interlevel insulator layer.Consequently, if the sum of the thicknesses of these three types ofsilicon oxide is less than 2 μm, formation of a thin film semiconductordevice by the low temperature process on large substrates is possiblewithout inducing cracking. Of course, it is possible to effectivelyprevent the generation of cracks if the sum of the thicknesses of theunderlevel protection layer, the gate insulator layer, and theinterlevel insulator layer is less than 2 μm.

[0031] As was explained previously in the reason for preferring the toplayer of the underlevel insulator layer to be of silicon oxide, whenusing a high-quality semiconductor film for the active layer such as inthe thin film semiconductor device of the present invention, control ofthe interface between the semiconductor layer and the underlevelprotection layer is important. Particularly when forming thesemiconductor layer using melt crystallization, it is desirable to havethe surface of the underlevel protection layer be as clean as possible.If the underlevel protection layer surface is clean, this not onlyreduces the number of interface states between the semiconductor layerand the underlevel protection layer, but also prevents particulate orother contaminants from being incorporated into the semiconductor layerduring the melt crystallization step. Therefore, it is beneficial if theunderlevel protection layer and the semiconductor layer can be formedsequentially in the same piece of equipment. If the underlevelprotection layer is silicon nitride, silicon oxide or a double layer ofboth, and the semiconductor layer is a silicon or silicon germaniumfilm, it is possible to sequentially form such layers using a singlePECVD reactor. If the mass production of thin film semiconductor devicesis considered, the deposition chamber for these films are periodicallycleaned; and it is necessary to remove the films which have adheredinside the PECVD deposition chamber. If cleaning is not carried out andthe films continue to adhere, the films may eventually peel off and fallor lead to generation of abnormal microparticles which result insignificant decreases in production yield. On the other hand, however,during the cleaning step to remove deposited thin films from thedeposition chamber, trace amounts of constituent elements from thecleaning vapors such as fluorine (F) and carbon (C) are sure to be leftbehind in the deposition chamber. Under these conditions, the traceelements can be incorporated as impurities into the semiconductor filmduring the deposition process and cause degradation of the transistorproperties. Additionally, if the cleaning process is repeated after aset number of substrates have been processed, the amount of impuritiesincorporated into substrates just after the cleaning step will be largewhile the amount incorporated into substrates just before the cleaningstep will be small. Put another way, the amount of impuritiesincorporated will differ from substrate to substrate; and it will not bepossible to reliably produce excellent thin film semiconductor devices.Consequently, in the present invention, the cleaning process isperformed as part of the sequential deposition of the films describedearlier. In other words, the cleaning process is included with the filmdeposition process for each substrate. As the first step, prior toplacing the substrate in the PECVD reactor, the deposition chamber iscleaned of any films which were deposited during processing of theprevious substrate. Specifically, cleaning gases such as NF₃, CF₄, CHF₃,CH₂F₂, and CH₃F are introduced into the deposition chamber separately,or in combination with such reaction-controlling gases as oxygen (O₂),hydrogen (H₂), or ammonia (NH₃) ; or, as need be, with such inert gasesas helium (He), argon (Ar), or nitrogen (N₂); and a plasma is initiated.Thin films deposited in the deposition chamber are removed in this step.Following completion of this cleaning procedure, a vacuum is pulled onthe chamber to remove as much of the remaining gas vapors as possible.Next, in step two, a silicon nitride or silicon oxide passivation layerfor the remaining impurity elements is deposited. The impurity elements,in other words, are sealed in by the passivation layer. As for the caseof the underlevel protection layer, a passivation layer of more than 100nm will effectively prevent the penetration of the impurities. It isnecessary to completely remove this passivation layer after theprocessing of each substrate. Therefore, since making the film too thickwill slow down the manufacturing process by increasing both the time forremoval in step one and the time for deposition in step two, the upperlimit for the passivation film thickness is approximately 1 μm. Whensilicon nitride is used as the passivation film, ammonia (NH₃) andsilane (SiH₄, Si₂H₆, etc.) are used as source gases. For silicon oxidepassivation layers, nitrous oxide (N₂O) and silane are used. Followingplacement of the substrate in the deposition chamber in step three, theunderlevel protection layer is grown on the substrate in step four. Thedeposited layer functions as the underlevel protection layer on top ofthe substrate but functions as a second passivation layer on areas inthe deposition chamber away from the substrate. Because the underlevelprotection layer by itself is able to prevent the diffusion ofimpurities within the underlevel layer, when combined with thepassivation layer deposited in step two, it is able to almost completelyprevent the incorporation of impurities into the semiconductor layer.Following step four, the semiconductor layer is grown in step fivewithout breaking vacuum; and the processing of a single substrate iscompleted with removal of the substrate from the deposition chamber instep six. The same procedure is repeated for each subsequent substrate.By following this substrate processing procedure and sequentiallydepositing the underlevel protection layer and the semiconductor layer,it is possible to keep the interface between the underlevel protectionlayer and the semiconductor clean and fabricate excellent thin filmsemiconductor devices. Further, it is possible to keep the amount ofimpurities such as fluorine and carbon incorporated in the semiconductorlayer to a minimum. Even if there are minute amounts within the films,since it is possible to always keep the amount constant, the result isthe ability to reliably produce excellent thin film semiconductordevices in a high productivity process.

[0032] (2-2, Semiconductor Films in the Present invention and the SourceGases used to Grow Them)

[0033] In the present invention, semiconductor films are deposited onsome type of substrates. This is a feature common to all the followinginventions. In addition to being applicable to single element films suchas silicon (Si) and germanium (Ge), the following types of semiconductorfilms are also possible: group IV compound semiconductor films such assilicon germanium, (Si_(x)Ge_(1-x): 0<×<1), silicon carbide(Si_(x)C_(1-x): 0<×<1), and germanium carbide (Ge_(x)C_(1-x): 0<×<1);III-V compound semiconductor films such as gallium arsenide (GaAs), andindium antimonide (InSd); II-VI compound semiconductor films such ascadmium selenide (CdSe). The present invention is also applicable tohigher compound semiconductor films such as silicon germanium galliumarsenide (Si_(x)Ge_(y)Ga_(z)As_(z): x+y+z=1) as well as N-typesemiconductor films in which donor elements such as phosphorous (P),arsenic (As), or antimony (Sb) have been added and P-type semiconductorsin which acceptor elements such as boron (B), aluminum (Al), gallium(Ga), and indium (In) have been added.

[0034] When semiconductor films are deposited by CVD in the presentinvention, the films are deposited using as source gases chemicalspecies containing the constitutive elements of the films. For example,when the semiconductor film is silicon (Si), a silane such as monosilane(SiH₄), disilane (Si₂H₆), trisilane (Si₃H₈), or dichlorosilane (SiH₂Cl₂)is used as a source gas. In the present invention disclosure, disilaneand trisilane are called higher silanes (Si_(n)H_(2n+2): n is an integergreater than or equal to 2). If germanium (Ge) is the semiconductorfilm, germane (GeH₄) is used; and phosphine (PH₃) and diborane (B₂H₆)can be used in addition if phosphorous (P) or boron (B) are to be addedto the semiconductor film. Although chemical species containing theconstitutive elements of the various types of films mentioned above canbe used as source gases, it is preferable to use hydrogenated species ofthe constitutive elements since some of the source gases will always beincorporated into the semiconductor film. For example, silicon filmsgrown from dichlorosilane (SiH₂Cl₂) will always contain some chlorine(Cl) whether in small or large amounts; and this incorporated Cl canlead to the degradation of transistor properties when the silicon filmis used as the active layer in a thin film semiconductor device.Therefore, monosilane (SiH₄), a hydrogenated form of the constituentelement, is preferable over dichlorosilane. As high a purity as possiblefor the source gases, and dilution gases if need be, is desirable.Considering that costs increase as the technological difficulties inproducing high purity gases grow, a purity of 99.9999% or higher isdesirable. The background pressure of common semiconductor filmdeposition equipment is on the order of 10⁻⁶ torr, and the processpressure is from 0.1 torr to a few torr. Therefore, the ratio of theincorporation of impurities from the background pressure in the filmgrowth step is on the order of 10⁻⁵ to 10⁻⁶. The purity of the source ordilution gases is sufficient if it is equivalent to the ratio of theprocess pressure to the background pressure of the equipment using thegases. As a result, a purity of 99.999% or more (impurity ratio of1×10⁻⁵ or less) for gases flowing in the deposition equipment isdesirable in the present invention. If the purity is 99.9999% (impurityratio of 1×10⁻⁶ or less), there is absolutely no problem for use as asource gas; and, in the ideal case in which the purity is ten times thatof the ratio of the background pressure to the process pressure(99.99999% in the present example; impurity ratio of 1×10⁻⁷ or less),the incorporation of impurities from the gases need not even beconsidered.

[0035] (2-3, LPCVD Reactor used in the Present Invention)

[0036] The LPCVD reactor used in the present invention to depositsemiconductor films by the LPCVD process will be explained. The LPCVDreactor can be either of the vertical or horizontal furnace type.Generally, the deposition chamber is made of quartz or like material,and the substrates are placed near the center region of the depositionchamber. The outside of the deposition chamber is divided into multiplezones with heaters located in each zone. A uniform thermal region iscreated at the desired temperature in the region around the centerportion of the reaction chamber by using these heaters which can beindependently controlled. This is a so-called hot wall LPCVD reactor. Byindependently controlling the individual heaters, it is possible to keepthe temperature variation within the uniform thermal region to within0.2° C. Even though this temperature variation is very slight, it isalways present, and is the leading cause of variations in filmthickness. Additionally, since film thickness uniformity over onesubstrate is given preference over film thickness from substrate tosubstrate, it is desirable to set the substrates parallel with respectto the radial heating direction of the heaters. For example, for avertical furnace LPCVD reactor, the semiconductor film thickness is moreuniform when the substrates are placed approximately horizontal asopposed to when they are placed vertically. Conversely, for a horizontalreactor, it is better to place the substrates approximately vertically.The source gases such as silane (SiH₄), disilane (Si₂H₆), or germane(GeH₄) and, when need be, dilution gases such as helium, nitrogen,argon, and hydrogen enter the deposition chamber from a gas introductionport set up in a given direction. After depositing a semiconductor layeron the multiple substrates set in the central region of the depositionchamber as well as on the side walls of the deposition chamber, thegases are exhausted from a location opposite to that of the entranceport. The gases are pumped through a gate valve or a conductance valveby a pumping system which may consist of a turbomolecular pump and arotary pump, for example. In the present invention, the pumping systemconsists of a turbomolecular pump and a rotary pump; but combinationswith mechanical booster pumps or dry pumps are also acceptable.Regardless of whether the reactor is vertical or horizontal, it isrelatively simple to achieve uniformity of the semiconductor film bybasically aligning the direction of gas flow in the deposition chamberwith the direction normal to the substrates set in the depositionchamber. In other words, in the case of a vertical reactor, it ispreferable to have vertical gas flow since the substrates are placedapproximately horizontally as mentioned previously. In a similarfashion, it is preferable to have horizontal gas flow in a horizontalreactor because the substrates are placed vertically. The LPCVD reactorused in the present invention is a high vacuum reactor with a backgroundpressure in the 10⁻⁷ torr range. Consequently, it is possible to pumpthe inevitable outgassing from the substrates and substrate boat at asufficient rate. The outgassing impurity species from the substrate andboat, which include water and oxygen among others, are impediments tothe growth of good semiconductor films. These outgassing impurities fromthe substrates and boat can become nuclei for the deposited film duringthe initial stages of deposition of a silicon or other type ofsemiconductor film. If the outgassing is not exhausted sufficiently,there will be a large amount of adsorbed impurity gases on the substratesurface leading to the generation of many nuclei. Even when thesemiconductor film is crystallized by thermal annealing or laserirradiation following deposition, the presence of the many nucleiresulting from the outgassing will result in the average grain size ofthe crystallized film being small and cause a degradation in thetransistor properties. Additionally, the trapping of outgassingimpurities in the semiconductor film during growth leads to furtherdecline in transistor properties. As explained in section (2-1), thefilm quality and surface roughness of the underlevel protection layerplay an important role in suppressing the generation of nuclei. At thesame time, the deposition conditions of the semiconductor film must alsobe carefully controlled. Consequently, in addition to the regulation ofthe surface of the underlevel protection layer in order to minimize thegeneration of nuclei, the use of an LPCVD reactor which can sufficientlypump the unavoidable outgassing from the substrates and the surroundingsurfaces is indispensable.

[0037] In LPCVD, semiconductor films are deposited on top of substratesusing thermal decomposition of the source gases. The two biggest issuesin using LPCVD to fabricate films on large substrates such as those 300mm ×300 mm at relatively low temperatures while maintaining highproductivity are the deposition rate (DR) and the uniformity. Forexample, consider the deposition of a silicon layer on a large area,conventional, low cost glass substrate as mentioned previously. Forsubstrates 300 mm ×300 mm or larger, distortion of the substrate fromits own weight will occur during film growth, regardless of the settingof the substrate, unless the deposition temperature is kept below about450° C. It goes without saying that such thermal distortion decreasesfor lower deposition temperatures; but for the distortion to decrease tosuch an extent that it has absolutely no effect on later process stepssuch as exposure during patterning, the deposition temperature must beless than about 430° C. Although semiconductor films such as silicon aredeposited at a low temperature of 425° C. using higher silanes likedisilane, decreasing the deposition temperature to such levels resultsin an extremely low deposition rate. Therefore, in order to obtain ahigh deposition rate even at such a low deposition temperature, thedeposition pressure is increased. Since gas density is proportional topressure, an increase in deposition pressure is equivalent to anincrease in the source gas density. The result is an increased rate oftransport of the source gases over the substrate surface and hence ahigher deposition rate. Unfortunately, however, using such a depositionprocedure causes the outer region of large substrates to be especiallythick; and the result is a deterioration in the film uniformity over thesurface of the substrate. The difference in film thickness between thecentral and outer portions of the substrate becomes conspicuous as thesubstrate size increases as well as when the deposition temperaturedecreases. One reason for this seems to be the generation of turbulenceat the substrate edge when the rate of source gas transport increases.As a result of the turbulence, a significantly large amount of gas istransported to only the edge regions with the final result being thatthe film is thicker along the edges as compared to the central portionof the substrate. Another reason seems to be that the transport rate ofthe gases to the center of the substrate decreases as the substrate sizeincreases. In other words, in order to obtain both a high depositionrate and uniform film thickness distribution at low temperatures lessthan 450° C. or less than about 430° C., it is essential to always havea high gas phase transport rate regardless of whether it is at the edgeor center of the substrate as well as to minimize the generation ofturbulence at the substrate edge. The inventor has performed a series ofexperiments which has shown that for a vacuum level characterized by asource gas partial pressure (disilane partial pressure if disilane isthe source gas) of between about 10 mtorr and 5 torr during deposition,the degree of turbulence and differences in transport rate are dependentupon the spacing, d, between substrates in the LPCVD reactor and can becontrolled to a certain degree. In the experiments, it was recognizedthat film thickness uniformity generally tended to improve as thesubstrate spacing d increased; and, further, that in order to obtain thesame level of uniformity for larger substrates, an even larger substratespacing was necessary. It appears that the uniformity improved as aresult of two phenomena. As the substrate spacing was increased by acertain degree, there was an increase in effective gas transport to thecenter region, and the difference in the amount of transport between thecentral and outer regions decreased. Additionally, the generation ofturbulence at the substrate perimeter also decreased. Specifically, inthe deposition temperature range of about 410° C. to 440° C., filmthickness uniformity can be improved by satisfying the conditions ofequation (1) shown below for substrates having an area greater than orequal to about 90000 mm² (substrate size of 300 mm ×300 mm):

[0038] ≧0.02×S^(1/2) (mm) . . . (1).

[0039] For example, a substrate spacing d of 6 mm or more for 300 mm×300mm substrates in a LPCVD reactor is good. Excluding the outer 1 cm of300 mm×300 mm substrates, the variation in film thickness was 3.4% whenthe substrates were set 7.5 mm apart in an LPCVD reactor for thefollowing deposition conditions: actual deposition temperature of 425°C., disilane flow rate of 200 sccm, helium flow rate of 1000 sccm,pressure of 1.2 torr, disilane partial pressure of 200 mtorr, and adeposition rate of 0.85 nm/min. (Film thickness variation is defined as(max−min)/(max+min) in which max and min are the maximum and minimumfilm thicknesses, respectively, in the 280 mm×280 mm area of thesubstrate which excludes the outer 1 cm around the perimeter.) Incontrast, a film thickness variation of 8.9% was obtained for thesame-size substrates under the exact same deposition conditions when thesubstrates were placed 5 mm apart in the LPCVD reactor. As will beexplained in another section, the semiconductor film thickness has astrong influence on the performance of the thin film semiconductordevices. As long as the film thickness variation is less than about 5%,however, there is essentially no problems in variation of deviceperformance. In a similar manner, while a film thickness variation of4.2% was obtained when 360 mm×465 mm substrates were loaded in the LPCVDreactor with a spacing of 10 mm, the variation was 10.1% for a spacingof 7.5 mm. According to equation (1), a substrate spacing of greaterthan or equal to 8.2 mm is necessary for 360 mm×465 mm substrates; andthis is faithfully supported by the actual results. In this manner, areactor with a 120 cm wide uniform thermal zone can process 100substrates if the substrates are spaced 10 mm apart even if dummysubstrates are placed one each at the top and bottom (or front andback). As will be explained in the following section, the processingtime for one batch using the deposition procedure in this invention ison the order of 3 hours. Consequently, the processing time for a singlesubstrate (called the tact time in this invention) is one minute and 48seconds. When LPCVD reactor maintenance and down time is added, the tacttime becomes 2 minutes. In other words, it is possible to fabricate thinfilm semiconductor devices with good thickness uniformity and highproductivity.

[0040] As mentioned previously, a decrease in deposition temperatureaccompanies a decrease in deposition rate and makes the attainment ofuniformity difficult. If the deposition temperature is less than about410° C., equation (2) below replaces equation (1):

[0041] d≧0.04×S^(1/2) (mm) . . . (2). If the substrates are setaccording to equation (2), good uniformity is possible just as in thecase of equation (1). As shown in FIG. 3(a), when two substrates areplaced back-to-back in a vertical configuration as one pair in ahorizontal LPCVD reactor for deposition of a semiconductor film, thedistance between adjoining pairs corresponds to the substrate spacing d.Considering the previous example of 360 mm×465 mm substrates, it becomespossible to process 200 substrates in a single batch; and, further, theproductivity is increased by a factor of two. A similar relationshipholds for vertical LPCVD reactors. In this case as well, two glasssubstrates are placed back-to-back as one pair and set approximatelyhorizontal. In other words, in one pair of glass substrates, the frontof the lower substrate is facing down while the front of the uppersubstrate is facing up. As for the case of the horizontal reactor, thespacing between pairs of substrates corresponds to the substrate spacingd. See FIG. 3(b). FIG. 4 shows one problem which occurs when largesubstrates are set horizontally in a hot-wall vertical LPCVD reactor.The center region of the substrate warps. This warp increases as thesubstrate size increases and also increases for lower glass strain pointsubstrates. Conversely, high strain point glass substrates with goodthermal resistance tend to have higher prices. As shown in FIG. 3(b),when setting several glass substrates in two-substrate pairs in an LPCVDreactor, semiconductor films are deposited using substrates withdifferent strain points paired together with the high strain point glasssubstrate used on the bottom. Because the high strain point glass haslittle warp, the low strain point glass substrate placed on top can alsobe made to have little warp using this technique. As a result, it ispossible to use even cheaper glass substrates. That is, pairing twoglass substrates not only simply increases the productivity by a factorof two, but also allows the price of one LCD to be easily reduced.

[0042] (2-4, LPCVD Semiconductor Film Deposition using the PresentInvention)

[0043] As explained in the preceding section, a deposition temperaturewhich is as low as possible is desirable for use with conventional,large area glass substrates. A decrease in deposition temperature,however, also means a decrease in deposition rate. In addition to theobvious decrease in productivity which results from the longer timenecessary for film deposition with a lower deposition rate, a slowerdeposition rate also has deleterious effects on thin film semiconductordevice performance. Put another way, in the fabrication of a good thinfilm semiconductor device with a silicon-containing semiconductor layerby the low temperature process, when depositing the semiconductor filmusing disilane or a higher silane at a deposition temperature less than450° C., especially less than or equal to approximately 430° C., if thedeposition rate is about 0.20 nm/min or higher, a high mobility thinfilm semiconductor device can be achieved. Further, if the depositionrate is about 0.60 nm/min or more, it is possible to decrease thevariation of transistor properties within a single substrate.Additionally, it is possible to fabricate a thin film semiconductordevice having good transistor properties using a poly-Si TFT in whichthe gate SiO₂ insulator layer is formed without the use of ECR-PECVD,and in which the pure silicon semiconductor film is deposited at adeposition temperature less than about 430° C. with a deposition rate ofabout 0.20 nm/min or more and is stable with respect to laser variationsduring melt crystallization. In fact, amorphous silicon films depositedat a deposition temperature of 400° C., disilane flow rate of 200 sccm,helium flow rate of 1000 sccm, pressure of 880 mtorr, disilane partialpressure of 147 mtorr, and a deposition rate of 0.12 nm/min as well asthose deposited at a deposition temperature of 425° C., disilane flowrate of 200 sccm, hydrogen flow rate of 200 sccm, pressure of 131 mtorr,disilane partial pressure of 65.5 mtorr, and a deposition rate of 0.19nm/min showed black spots throughout transmission electron micrographsand had small grain sizes following crystallization by RTA. As a result,the mobilities were also low when these films were employed as theactive layer in transistors. Although the details may not be certain,the following explanation may explain why black spots are seen intransmission electron micrographs and transistor properties degrade whenfilms are deposited with a deposition rate less than 0.20 nm/min.Perhaps if the growth rate is excessively slow, the surface of thegrowing film is exposed for a longer time to the gas phase with theresult being that more impurities from the background vacuum areincorporated. Therefore, the lower limit of the deposition rate dependson the background pressure in the LPCVD reactor. In other words, in anLPCVD reactor with a background pressure of 1×10⁻⁷ torr to 1×10⁻⁶ torrsuch as the one in the present invention, a good semiconductor film canbe deposited if the deposition rate is greater than or equal to 0.20nm/min. If the deposition rate becomes greater than or equal to 0.60nm/min, the effects from gas impurities disappear completely; and theamount of variation in transistor properties decreases as well. Further,as will be explained later, the optimum film thickness of thesemiconductor film for a thin film semiconductor device formed by LPCVDin the present invention is about 50 nm. Therefore, the deposition timeis on the order of 80 minutes for a deposition rate greater than orequal to 0.60 nm/min. Including the approximately 20 minutes necessaryto insert the substrates in the LPCVD reactor and pull a vacuum, theapproximately one hour for preliminary heating prior to film growth, theaforementioned one hour and 20 minutes for deposition, and theapproximately 20 minutes necessary for pulling a vacuum after filmgrowth and unloading the substrates, the total processing time for onebatch is about three hours. As shown in the previous section, the tacttime for processing a batch of 100 substrates is about two minutes; andextremely high productivity with a tact time of less than one minute canbe realized if the method of pairing two substrates together is used.

[0044] As has been explained in the preceding sections, in order toreliably fabricate a high performance poly-Si TFT on large substrateswith the low temperature process, a silicon-containing semiconductorfilm deposition temperature of less than approximately 430° C.,deposition rate greater than or equal to 0.6 nm/min, and, a filmthickness variation of less than about 5% over a large substrate areideally required. For the case in which a higher silane such as disilaneis used as the source gas in film formation using LPCVD, theseconditions can be satisfied by a providing a relationship between thetotal surface area A (cm²) inside the LPCVD) reactor which can becovered with the semiconductor film and the flow rate Q (sccm) of thehigher silane introduced into the deposition chamber during growth. Inother words, by controlling the higher silane flow rate per unit area, R(sccm/cm²) which is given by

[0045] R=Q/A, it is possible to satisfy the three ideal conditionsmentioned above. in the growth of semiconductor films by LPCVD, thedeposition temperature mainly determines the chemical reaction rate atthe surface of the substrates. On the other hand, there is a positivecorrelation between the spatial concentration of the source gas and therate of transport of the source gas in the gas phase. The concentrationof the source gas C is related to the source gas pressure P and thetemperature T_(g) by

[0046] C=P/kT_(g) in which k is the Boltzmann constant. When furtherincreasing the deposition rate with the deposition temperature set at afixed value, that is, with the potential rate of surface reaction fixed,it is common to increase the actual surface reaction rate by increasingthe source gas pressure P to increase the rate of transport in the gasphase. But, as mentioned previously, increasing the deposition rate byincreasing the pressure unfortunately harms the film thicknessuniformity. While this fact is recognized, the pressure inside thedeposition chamber P is related to the pumping speed S and the gas flowrate Q by

[0047] P=Q/S. Here there are three independent variables related by asingle equation which results in the existence of two independentvariables. in other words, if only pressure P is fixed, it is notpossible to determine a single physical condition. This means that foran identical pressure of 100 mtorr, a system with a gas flow rate of 100sccm and a pumping speed of 1 sccm/mtorr is completely different than asystem with a gas flow rate of 1 sccm and a pumping speed of 0.01sccm/mtorr. The inventor noticed this fact, and examined what kind ofeffect changes in the deposition chamber pumping speed and the disilanesource gas flow rate had on the deposition rate and the film thicknessuniformity while keeping the deposition temperature and depositionpressure constant. The results showed that even for a fixed depositiontemperature and deposition pressure, the deposition rate increased alongwith increases in source gas flow rate; and further that the filmthickness uniformity was improved. Additionally, this relationship wasrecognized to be strongly related to the total surface A inside thereaction chamber; and that it is necessary to increase the source gasflow rate in proportion to the total surface area. This will beexplained using FIG. 5. Amorphous silicon films were deposited in a184.51 vertical, hot wall LPCVD reactor with thirty five 300 mm×300 mmsubstrates placed a distance of 10 mm apart. The total surface area ofthe 35 substrates was 63000 cm² since the area of one substrate (frontand back) is 30 cm×30 cm×2 or 1800 cm². Since the surface area ofregions inside the reactor which can be coated with the semiconductorfilm during deposition is 25262 cm², the total surface area which can becoated inside the reactor is

[0048] A=63000+25262=88262 cm². Under these conditions, semiconductorfilms were deposited by flowing only disilane into the depositionchamber at a deposition temperature of 425° C. and a deposition pressureof 320 mtorr. The disilane flow rate was varied from 50 sccm to 400 sccmwhile the deposition pressure was kept constant at 320 mtorr by varyingthe deposition chamber pumping speed by means of the LPCVD reactorpressure control unit. The deposition rate as a function of disilaneflow rate under the given conditions is shown by the circular datapoints and the “DR” solid line in FIG. 5 while the film thicknessvariation is shown by the square data points and the “V” dashed line.Since A is 88262 cm², the corresponding R values for the given flowrates, Q, are: Q=50 sccm, R=5.66×10⁻⁴ sccm/cm²; Q=100 sccm, R=1.13×10⁻³sccm/cm²; Q=200 sccm, R=2.27×10⁻³ sccm/cm²; and Q=400 sccm, R=4.53×10⁻³sccm/cm². For R greater than 2.27×10⁻³ sccm/cm², the deposition rate isessentially saturated; and the surface reaction rate and the potentialrate of surface reaction nearly agree. As discussed previously, for afixed deposition temperature and deposition pressure, a higherdeposition rate is preferred from both the viewpoint of productivity andthe viewpoint of semiconductor film quality. When the deposition rate ishigh, the film growth rate is large compared to the nucleation rate sothat both the grain size in the films after crystallization increasesand the amount of impurity gases from outgassing incorporated into thefilm is decreased. Both of these factors lead to improvement in thesemiconductor film quality and mean increases in mobility and decreasesin threshold voltage when these films are used as the active layer inthin film semiconductor devices.

[0049] Additionally, the decrease in impurity incorporation leads tosuppression of the poly-Si TFT off current. On account of these factors,a high deposition rate is preferred, and as seen in FIG. 5, this valuesaturates for R greater than or equal to 2.27×10⁻³ sccm/cm².Consequently, a value of the higher silane flow rate per unit area ofabout 2.27×10⁻³ sccm/cm² or more is preferred for the deposition ofsemiconductor films. The present experiment was performed in a verticalreactor with the gas introduced from the top and exhausted from thebottom. Using R=5.66×10⁻⁴ sccm/cm² resulted in a difference indeposition rate of 18% between the upper most substrate and the lowermost substrate. For R greater than or equal to about 1.13×10⁻³ sccm/cm²,this difference was practically unobservable; and, therefore, to obtainuniformity among substrates, an R value greater than or equal to about1.13×10⁻³ sccm/cm² is desirable. Further, as seen in FIG. 5, anR≧4.54×10⁻³ sccm/cm² is ideal since the variation within a singlesubstrate is 5% or less and gives a high deposition rate of 1.30 nm/min.

[0050] The source gas flow rate which corresponds to the total surfacearea in the LPCVD reactor which can be covered with a semiconductor filmmust also be varied. In other words, the parameter which must becontrolled is the higher silane flow rate per unit area, R. The exactsame experiment described above was repeated with seventeen 235 mm×235mm substrates placed a distance of 20 mm apart in the LPCVD reactor. Thesubstrate area was 23.5 cm×23.5 cm×2×17=18777 cm². This was combinedwith the reactor area of 25262 cm² to yield a total surface area of44039 cm². R values of about 5.66×10⁻⁴ sccm/cm², 1.13×10⁻³ sccm/cm²,2.27×10⁻³ sccm/cm², and 4.53×10⁻³ sccm/cm² correspond to higher silaneflow rates of 25 sccm, 50 sccm, 100 sccm, and 199 sccm, respectively.When the deposition rate and film thickness uniformity among substrateswas examined for the given disilane flow rates, behavior identical tothat found previously was confirmed. That is, in addition to thedeposition temperature and deposition pressure, the higher silane flowrate per unit area is a parameter necessary to unambiguously define thephysical system. According to the discovery above, an R value of about1.13×10⁻³ sccm/cm² or more is required for the deposition of asilicon-containing film at a deposition temperature of about 430° C. orless and a disilane partial pressure of about 100 mtorr or more. Forexample, for the deposition of a semiconductor film using one hundred400 mm×500 mm substrates set 15 mm apart in a 900 mm diametercylindrical deposition chamber, the substrate surface area is 400000cm²; and the surface area inside the deposition chamber is about 56550cm², leading to a total surface area A of about 45650 cm². Therefore,the minimum necessary silane flow rate is given by the R value of1.13×10⁻³ sccm/cm² multiplied by the area A or 518 sccm. Similarly, aminimum flow rate of about 1050 sccm is necessary for semiconductor filmdeposition in the case in which there are one hundred 560 mm×720 mmsubstrates placed 25 mm apart in a 1200 mm diameter chamber since A isapproximately 919500 cm² and R≧1.13×10⁻³ sccm/cm².

[0051] (2-5, Poly-Si TFT Channel Layer Thickness and TransistorProperties)

[0052] Here, the relationship between the semiconductor film thicknessof the active layer forming the channel in a poly-Si TFT thin filmsemiconductor device and the transistor properties will be discussed.Generally, the optimum film thickness for the semiconductor film to beused as the channel in a thin film semiconductor device depends stronglyon the fabrication method. This is because the film quality of thesemiconductor film varies widely with the film thickness. For example,in systems such as SOS (silicon on sapphire) and SOI (silicon oninsulator) in which the film quality does not, as a rule, depend on thefilm thickness, the transistor properties improve for thinnersemiconductor films. (Here, this principle is called the thin filmeffect.) This is because the inversion layer quickly spreads throughoutthe entire film thickness and the inversion layer can form readily inthe case of thin semiconductor films (the threshold voltage Vthdecreases). On the other hand, in thin film semiconductor devices usingpolycrystalline silicon films for the channel layer, the quality of thesemiconductor film is vastly different depending on the film thickness;and the mechanism mentioned above is much more complicated. Usually, thefilm quality of polycrystalline films worsens as the film thicknessdecreases. Specifically, in comparison to thick films, the grain size inthin films is smaller; and the number of internal grain defects andgrain boundary traps is simultaneously large. If the grain size issmall, the mobility of thin film semiconductor devices using such filmswill be low. Additionally, if the number of internal grain defects andgrain boundary traps is large, the spread of the depletion layer slows;and the threshold voltage Vth increases substantially. (Here, thisprinciple is called thin film degradation.) Ultimately, the thin filmeffect mentioned earlier and thin film degradation are competingprocesses. If the films are made thin but there is little change in filmquality (thin film degradation is small), the thin film effect isapplicable; and the transistor properties improve with thinner films.Conversely, if the films are made thin and there is a remarkabledegradation of the film quality (thin film degradation is large), thethin film effect is canceled; and transistor properties worsen forthinner films. In other words, depending on the magnitude of the filmquality dependence on the film thickness, the transistor properties mayimprove or may worsen with the use of thinner films. This dependence offilm quality on film thickness differs depending on fabricationtechnique; and also differs depending on film thickness. Consequently,the optimum semiconductor film thickness is completely differentdepending on the fabrication process of the thin film semiconductordevice; and the optimum thickness value must be determined for eachfabrication process.

[0053] (2-6, Optimum Film Thickness for the LPCVD-CrystallizationMethod)

[0054] Here, the optimum poly-Si-TFT semiconductor film thickness for asemiconductor film fabricated by first using LPCVD at a depositiontemperature less than about 450° C., ideally about 430° C. or less,followed by crystallization for use in a low temperature process thinfilm semiconductor device of the present invention as described above isexplained. Using LPCVD at less than about 450° C., or less than or equalto about 430° C., the deposited film can coalesce to form a continuousfilm when the film thickness reaches approximately 10 nm or more. If acontinuous film does not form but only island regions exist, thesemiconductor “on” characteristics will be extremely poor because thefilm will still be discontinuous after crystallization regardless of theuse of melt crystallization or solid phase crystallization. In short,thin film degradation has overwhelmingly defeated the thin film effect.Therefore, the minimum film thickness for LPCVD-crystallization is onthe order of about 10 nm. As film thickness reaches about 20 nm or more,the transistor properties of melt crystallized films begin to improve.In the melt crystallization of semiconductor films, crystallizationoccurs with the gathering of peripheral semiconductor atoms around asingle central nucleus during the cooling solidification stage. Becauseof this, when film thickness is less than about 20 nm, even if acontinuous film forms immediately after deposition by LPCVD, cracks andcrevices are generated throughout the film following meltcrystallization; and transistor properties still do not improve. Inother words, in LPCVD-melt crystallization, thin film degradationdominates for films less than about 20 nm. As the film thickness reachesmore than about 20 nm, thin film degradation gradually decreases; andthe thin film effect begins to rival thin film degradation. Continuingthe trend in increased film thickness, transistor properties are bestfor film thickness between about 20 nm and about 80 nm. For thicknessesgreater than about 80 nm, the thin film effect predominates, andtransistor properties deteriorate along with increases in filmthickness. For semiconductor films about 30 nm or thicker, stable andreliable production is possible. Particularly with the advance of highprecision processing, the problem of contact failure between thesemiconductor film and the metallization can be decreased significantlyfor films approximately 30 nm or thicker when such processes as reactiveion etching (RIE) are used to open contact holes in the interlevelinsulator layer or the gate insulator layer. Usually the combinedthickness of the gate insulator layer and interlevel insulator layer isabout 600 nm; and if the film thickness variation for this thickness is±10%, or a total of 20%, the difference in film thickness between thethinnest insulator layer and the thickest insulator layer is on theorder of 120 nm. Since the selectivity ratio of RIE with respect tosemiconductor films is about 1:10, approximately 10-15 nm of thesemiconductor layer lying beneath the thinnest insulator layer isremoved during the opening of contact holes in the thickest insulatorlayer. Thus, even if about 15 nm is lost in such a manner during theopening of contact holes, the contact resistance is sufficiently low andthe problem of contact failure does not occur if the semiconductor filmthickness is about 30 nm or more. If the semiconductor film thickness isless than or equal to about 70 nm, the entire semiconductor layer can beuniformly heated and crystallization can proceed smoothly during meltcrystallization using a laser or other means. If, however, the filmthickness is greater than about 140 nm, only the upper portion of thelayer is melted during laser irradiation from above and the bottomportion of the layer retains amorphous regions. This adds to the thinfilm effect and the transistor properties deteriorate profoundly. Inother words, the maximum film thickness for the LPCVD-crystallizationmethod is on the order of 140 nm.

[0055] (2-7, Semiconductor Film Deposition Using the PECVD Process ofthis Invention)

[0056] The method of forming the semiconductor film of the thin filmsemiconductor device of this invention using the PECVD process will bedescribed. The PECVD reactor used here is the capacitively-coupled type.The plasma uses industrial frequency rf waves (13.56 MHZ) and isgenerated between two parallel plate electrodes. Of the two parallelplate electrodes, the lower parallel plate electrode has groundelectrical potential. The substrate on which the semiconductor film isto be deposited is placed on this electrode. The rf waves are suppliedto the upper parallel plate electrode. In addition, multiple gasintroduction ports exist in the upper parallel plate electrode, and thesource gases are supplied in a uniform laminar flow from this electrodeto the deposition chamber. The pressure at the time the film formationtakes place is from approximately 0.1 torr to approximately 5 torr. Thedistance between the parallel plate electrodes can be varied from about10 mm to about 50 mm.

[0057] After forming the underlevel protection layer on at least aportion of the substrate surface using an insulating material, such as asilicon oxide film, a semiconductor film is formed on top of thisunderlevel protection layer. Ultimately, a thin film semiconductordevice that uses the semiconductor film as the transistor's active layerwill be produced. When a semiconductor film is to be deposited using thePECVD process, initially the underlevel protection layer is exposed toan oxygen plasma after the substrate has been placed in the depositionchamber of the PECVD reactor. The oxygen plasma is generated at anelectrode spacing of about 15 mm to 35 mm, a pressure of about 1.0 torrto 2.0 torr and an rf power density of approximately 0.05 w/cm² to 1w/cm². The temperature of the substrate is the same 250° C. to 350° C.as that during semiconductor deposition, and the oxygen plasma exposuretime is from about 10 seconds to one minute. After exposure to theoxygen plasma, the plasma is temporarily stopped and the depositionchamber is pumped down for 10 seconds to 30 seconds. If the vacuumpump-down takes place for 15 seconds or more, the level of the vacuum inthe deposition chamber will be 1 mtorr or lower. This takes place toprevent oxygen from being incorporated into the semiconductor filmduring semiconductor film deposition in the subsequent process step.After pulling the vacuum, the source gases that are used forsemiconductor film deposition, such as silane and hydrogen, are allowedto flow for 10 seconds to two minutes without generating a plasma.During this time, the conditions inside the deposition chamber, such asthe pressure and source gas flow rate, are the same as those used duringsemiconductor film deposition. Because this will result in the oxygen inthe deposition chamber being entirely replaced by the source gas, theincorporation of oxygen into the semiconductor film will be minimized.Further, if the period of gas flow is 30 seconds or more, thetemperature of the substrate is maintained at a constant temperature,and the semiconductor film can always be deposited under the sameconditions. In the thin film semiconductor device of this invention, theupper-most layer of the underlevel protection layer is composed of afilm such a silicon oxide, which has a low nucleation rate. Since thissilicon oxide film is formed using the CVD process or the PVD process,there will always be dangling bonds of the silicon. For this reason, ifthe semiconductor film is formed on top of the underlevel protectionlayer without some kind of pre-treatment, the dangling bonds would actas fixed electrical charges within the underlevel protection layer. Aspreviously stated, when the semiconductor film is thin, at or below afew hundred nanometers, these fixed electrical charges will causenegative influences on the thin film semiconductor device, such ascausing variations in the threshold voltage (Vth). By applying an oxygenplasma to the surface of the underlevel protection layer, the danglingbonds will bind with the oxygen atoms, and thus drastically reduce thefixed electrical charges within the underlevel protection layer. Inother words, even though the semiconductor film is made thin enough toimprove the semiconductor properties, instabilities in the properties,such as the Vth fluctuations caused by the underlevel protection layer,can be resolved. Moreover, the exposure to oxygen plasma will clean thesurface of the underlevel protection layer through the oxidationreaction (combustion) and restrain even further the nuclei generationrate at the initial stage of semiconductor deposition. This willincrease the purity of the semiconductor film, enlarge the areas thatform the deposited film, and enlarge the crystal grains that form thecrystallized semiconductor film. In terms of the properties of the thinfilm semiconductor device, this is manifest as a decrease in the offcurrent, a reduction in Vth, an improvement in the switching propertiesbecause sub-threshold swing will steepen, and an increase in themobility.

[0058] To improve the underlevel protection layer surface, in additionto exposure to an oxygen plasma, exposure to a hydrogen plasma is alsoeffective. That is, after the substrate on which the semiconductor filmis to be deposited is placed inside the PECVD reactor, the underlevelprotection layer on the substrate is first exposed to a hydrogen plasma.Then, without breaking vacuum, the semiconductor film is sequentiallyformed on top of the underlevel protection layer. The semiconductordeposition conditions use a lot of hydrogen, as in hydrogen 3000 sccmand monosilane 100 sccm. Furthermore, when the ratio of hydrogen is 10times or more that of silane, it is also possible to have continuousprocessing, from hydrogen plasma processing to semiconductor filmformation, without stopping the plasma. When the semiconductor filmdeposition conditions differ from the hydrogen plasma conditions, aswith monosilane 100 sccm in argon 7000 sccm, the plasma is temporarilyterminated after the hydrogen plasma processing; and, except for thefact that the plasma is not generated, it is desirable to have all otherprocess parameters the same as for the semiconductor film depositionconditions in order to create a stabilization period before thedeposition. Doing so will allow the substrate temperature to always beconstant when the semiconductor film is deposited. The hydrogen plasmaprocessing time is from 10 seconds to one minute, and the stabilizationperiod before the semiconductor film deposition is from 10 seconds totwo minutes.

[0059] Of the dangling bonds in the underlevel protection layer, thereare those that are terminated by oxygen, as in Si-*, and those thatcannot be terminated by oxygen, as in Si-O-*. Because hydrogen plasmaexposure can terminate these dangling bonds in the form of Si-H andSi-OH, an extraordinary effect can be observed in the decrease in thefixed electrical charges in the underlevel protection layer. Inaddition, because hydrogen plasma processing also has the effect ofetching and cleaning the underlevel protection layer surface, it alsoincreases the purity of the semiconductor film. Further, the adhesion ofthe underlevel protection layer and the semiconductor film improvesdramatically as a result of this cleaning. When a semiconductor film isformed using the PECVD process, crater-shaped holes can be generated inthe semiconductor film; and the film sometimes peels off depending onthe deposition conditions. This can be prevented, however, by processingwith hydrogen plasma.

[0060] When a semiconductor film is deposited, it is even more desirableto process with both oxygen plasma and hydrogen plasma. In other words,initially expose the surface of the silicon oxide underlevel protectionlayer to an oxygen plasma. At first, dangling bonds in the underlevelprotection layer will be terminated by the oxidation reaction. At thesame time, the surface will be cleaned by means of combustion, and thiswill suppress the rate of nuclei generation. Next, the oxygen plasma isterminated, and a vacuum is pulled for a period of from about 10 secondsto one minute to remove the oxygen within the deposition chamber. Theunderlevel protection layer is then sequentially exposed to a hydrogenplasma without breaking vacuum. Some dangling bonds that could not beterminated with the oxygen plasma will be terminated with the hydrogenplasma, and this will reduce the fixed electrical charges in theunderlevel protection layer to a minimum. Moreover, the surface willbecome even cleaner and at the same time the adhesion between thesemiconductor film and the underlevel protection layer will alsoimprove. After processing with the hydrogen plasma, vacuum pump-down andsubstrate heating will take place as needed; and the semiconductor filmis formed on the underlevel protection layer sequentially withoutbreaking vacuum. Doing this will not only bring about both thepreviously mentioned oxygen plasma effect and hydrogen plasma effect,but there will also be a clear reduction in the amount of oxygenincorporation into the semiconductor film since the hydrogen plasma stepcomes between the oxygen plasma step and the formation of thesemiconductor film. This will also allow a higher purity and higherquality semiconductor film to be obtained. As stated in section (2-1),for a melt crystallized semiconductor film, a clean underlevelprotection layer surface and control of the underlevel protectionlayer-semiconductor interface are particularly important. Consequently,the underlevel protection layer surface processing prior tosemiconductor film deposition is exceptionally significant.

[0061] Next, the processing after the semiconductor film has been formedusing the PECVD process will be described. After the semiconductor filmhas been formed on top of the underlevel protection layer, it isdesirable to sequentially expose the semiconductor film to a plasmawithout breaking vacuum. This will terminate the dangling bonds of thesemiconductor atoms, such as those of silicon. This is particularlyeffective when the film is formed under conditions in which there islittle hydrogen when the semiconductor film is deposited. For example,it is particularly effective in a system in which the amount of hydrogenis less than 50 percent of the gases that are introduced to thedeposition chamber, such as when the semiconductor film is depositedusing silane mixed with inert gases such as helium or argon. When asemiconductor film is deposited using such a system, a huge number ofdangling bonds will exist in the film. Since these dangling bonds areextremely chemically active, they will react with a variety ofimpurities and substances that exist within the atmosphere, or thesematerials can physically adsorb. If crystallization takes place in sucha condition using a laser, for example, the purity of the semiconductorwill decrease. In addition, the grains will become smaller since theadsorbed substances become the nuclei for crystal growth. Such problempoints can be easily eliminated by hydrogen plasma processing. In otherwords, a high purity, high-quality semiconductor film is in and ofitself unstable and can be contaminated by the atmosphere. Such a highpurity, high-quality film, however, can be stabilized by applying ahydrogen plasma after the film has been formed.

[0062] After the semiconductor film has been formed on top of theunderlevel protection layer, the same type of effect can also beaccomplished by sequentially exposing the semiconductor film to anoxygen plasma without breaking vacuum. When the semiconductor film issilicon or when silicon is the main component, oxygen plasma will form asilicon oxide film on the semiconductor film surface. This oxide film isextremely stable. Compared to the semiconductor film surface, itsability to prevent chemical and physical contaminant adsorption as wellas diffusion of such contaminants to the semiconductor film isexcellent. That is, it is optimal for protecting the semiconductor filmfrom external contaminants. Further, because the oxidation takes placeusing an oxygen plasma in which the oxygen is quality-adjusted for highpurity as opposed to oxygen in the atmosphere, the purity of the oxidefilm itself is high. During subsequent crystallization, it is desirableto remove the oxide film. Yet, even if the oxide film is not removed,there are virtually no problems with contaminants from the oxide filmbeing incorporated into the semiconductor film.

[0063] Ideally, after the semiconductor film has been deposited using aPECVD reactor, the film is exposed to a hydrogen plasma sequentiallywithout breaking vacuum, and this will inactivate most of the danglingbonds by hydrogen termination. Subsequent to this and again sequentiallywithout breaking vacuum, the semiconductor film is exposed to an oxygenplasma. This oxygen plasma will terminate any dangling bonds that werenot terminated by the hydrogen plasma and can also be expected to formon the surface of the semiconductor film a highly pure silicon oxidefilm that protects the semiconductor film from external contamination.Using this method of processing, not only will both the hydrogen plasmaeffect and the oxygen plasma effect be obtained, but also the effect ofthe dangling bond termination will increase and the amount of oxygenincorporated into the semiconductor film can be reduced. As a result,the semiconductor film purity after the crystallization will increasemore so than processing with the oxygen plasma alone, forming a betterthin film semiconductor device.

[0064] In the oxygen plasma exposure stage, as stated previously,regardless of the LPCVD and PECVD processes and even if the greatestamount of care is taken so that the semiconductor film becomes verypure, because an oxide film exists on the surface of the semiconductorfilm, the quality of the crystallized film will decrease if oxygen isincorporated into the semiconductor film during crystallization. Thissituation becomes particularly serious in the case of meltcrystallization such as by laser irradiation.

[0065] A semiconductor film which has been carefully prepared usingunderlevel protection layer surface preparation and the LPCVD and PECVDprocesses, as in this invention, requires that the same type of care betaken when crystallizing. In other words, when a semiconductor film thatforms the active layer of a thin film semiconductor device is formed bymelt crystallization, such as by laser irradiation, it is desirable toremove the oxide film from the semiconductor film surface immediatelyprior to melt crystallization. Doing so will allow the amount of oxygenfrom the oxide layer that gets into the semiconductor film to be reducedto a minimum when semiconductor film melting occurs. If the amount ofoxygen that gets into the semiconductor film is reduced, not only willthe crystallinity of the crystallized film increase, the defect densitywill decrease and the transistor properties will greatly improve.

[0066] The processing method that makes the removal of the oxide filmimmediately prior to crystallization the easiest is one that uses ahydrofluoric acid solvent. Of course, the oxide film can be removed by agas-phase plasma process such as by using an NF₃ plasma. It is desirableto crystallize the semiconductor film immediately after removing theoxide film. If the semiconductor film is melt crystallized within twohours of the completion of the oxide film removal process, the amount ofoxygen that gets into the semiconductor film will be extremely low.

[0067] (2-8, Melt Crystallization of a Mixed-Crystallinity SemiconductorFilm)

[0068] The thin film semiconductor device of this invention is mosteffective for top-gate poly-Si TFTs which are produced at temperaturesof 350° C. or lower for all process steps from the formation of the gateinsulator layer forward. As a consequence, if the semiconductor filmformation step can take place at a temperature of 350° C. or lower, allof the process steps will take place at 350° C. or lower. Currently, thethickness of the conventional glass substrates for LCDs is 1.1 mm. Ifthis were 0.7 mm, however, not only would the glass substrates becomecheaper, but also major benefits in the portability and the productionof the LCDs would arise because of the lighter-weight substrate. Sincethe density of glass is approximately 2.5 g/cm³, the weight of one sheetof glass with dimensions of 400 mm×500 mm x_(—)1.1 mm, for example, isabout 550 grams. If such glass substrates were processed in batches of100 sheets, the weight would be 55 kg, which would be a large load forproduction equipment and for transport robots. It goes without sayingthat if the thickness were 0.7 mm, the weight of a batch would decreaseto 35 kg, significantly reducing the load. For this reason, thinning ofthe glass substrates is desirable. Such a large thin film glass wouldbow significantly under its own weight, however, even at roomtemperature as shown in FIG. 4. And no matter what method were used withthe LPCVD process, a semiconductor film could not be formed. In otherwords, in order to use such a large piece of thin glass, thesemiconductor film would have to be formed using the PECVD process at atemperature of 350 degrees C. or lower. Yet, in general, because of lowdensity of the films and the large amount of incorporated hydrogen, anamorphous semiconductor film formed using the PECVD process cannotcrystallize unless it first undergoes thermal annealing at 450° C.

[0069] When the inventor conducted various studies of semiconductorfilms from the PECVD process, it was discovered that when using thePECVD process at a deposition rate of about 0.1 nm/s or higher, amixed-crystallinity semiconductor film was produced and when thismixed-crystallinity semiconductor film was exposed to laser light, meltcrystallization was possible even without the thermal annealing stepmentioned above. Although the existence of crystal structure in thismixed-crystallinity film can barely be observed by Raman spectrometry,for instance, it is difficult to call the film polycrystalline. Inaddition, the density is as low as the amorphous silicon formed usingthe PECVD process of the prior art, and hydrogen atoms are contained atjust under 20 percent of the silicon atoms. The details of why such afilm can be melt crystallized in an orderly manner are not known. But itis believed that it might be that the amorphous region is more easilymelted than the microcrystalline region, and that the microcrystals thatfloat in the melted silicon liquid play the role of restricting theevaporation and the scattering of the melted silicon liquid. Yet, evenfor a mixed-crystallinity semiconductor film, it is difficult to meltcrystallize such a film with a deposition rate of about 0.1 nm/s orlower. As in the case with LPCVD in which it seems that film qualitydecreases for slower deposition rates as a result of the increased easeof impurity incorporation, the incorporation of impurities during filmgrowth in PECVD also seems to be the main factor leading to difficultiesin crystallization. In contrast to a background vacuum pressure in the10⁻⁷ torr range using LPCVD reactors, the background vacuum pressure isin the 10⁻⁴ torr range in PECVD reactors, and this may be the reasonthat high-speed film deposition can be observed using PECVD. Inaddition, if the deposition rate was 0.37 nm per second or higher, therewas an improvement in the adhesion between the semiconductor film andthe underlevel protection layer; and the generation of crater-shapedholes and film peeling virtually disappeared. Using the PECVD process, amixed-crystallinity silicon film can be obtained by setting the ratio ofthe hydrogen to monosilane flow rates to approximately 30:1.Alternatively, a mixed-crystallinity silicon film can be obtained bysetting the ratio of the flow rates of inert gases like argon to that ofthe chemical specie containing the constitutive elements of thesemiconductor film, such as monosilane, to less than about 33:1 (lessthan about 3 percent monosilane concentration). Based on experiments bythe inventor, hydrogen-monosilane system mixed-crystallinity can also bemelt crystallized without thermal annealing. The laser energy range inwhich melt crystallization proceeds well, however, is limited to severaltens of mJ/cm². In contrast to this, an argon-monosilane systemmixed-crystallinity silicon film will crystallize smoothly in a widelaser energy region, from 100 mJ/cm² to 350 mJ/cm². Therefore, anargon-monosilane system mixed-crystallinity silicon film is moresuitable as the semiconductor film of low temperature process poly-SiTFTs. The optimal argon to monosilane flow ratio for meltcrystallization is from about 124:1 (approximately 0.8 percentmonosilane concentration) to about 40.67:1 (approximately 2.4 percentmonosilane concentration).

[0070] (2-9, Optimum Film Thickness of PECVD-Crystallized Films)

[0071] Here, the optimum semiconductor film thickness for a poly-Si TFT,of a low temperature process thin film semiconductor device of thepresent invention described above, that was fabricated throughcrystallization after the semiconductor film was formed using the PECVDprocess at a deposition temperature of 350° C. or lower will bedescribed. Among the low temperature process thin film semiconductordevices of this invention that have been discussed above, here will bedescribed. In the PECVD process, as in the LPCVD process, a film willbecome continuous when it reaches a thickness of 10 nm or more. However,the density of the semiconductor film obtained using the PECVD processis from approximately 85% to 95% of the film density obtained using theLPCVD process. For this reason, if the 10 nm semiconductor film of thePECVD process is crystallized, its film thickness will fall to about 9nm after crystallization. Thus, the minimum film thickness of aPECVD-crystallized film will be approximately 9 nm. As withLPCVD-crystallized films, if the film thickness is about 18 nm or more,the transistor properties of the melt crystallized film will begin toimprove. That is, with PECVD-melt crystallization, at 18 nm or less,thin film degradation is dominant; and, at 18 nm or higher, thin filmdegradation decreases, and the thin film effect becomes competitive.This will continue if the film thickness is between approximately 18 nmand approximately 72 nm and the transistor properties are optimum forfilms within this thickness range. If the film is thicker than 72 nm,the thin film effect takes control and the transistor properties willgradually deteriorate as the thickness of the film increases. If thesemiconductor film thickness is 30 nm or more, it is possible to havestable production of highly integrated thin film semiconductor devicesthat require fine geometry fabrication. In other words, with RIE,contacts holes can be opened up reliably without the appearance ofcontact failure. If the semiconductor film thickness immediately afterdeposition using the PECVD process is about 80 nm or less, the entiresemiconductor layer can be uniformly heated and crystallization canproceed smoothly during melt crystallization using a laser or othermeans. After crystallization, the thickness of the film will beapproximately 72 nm. If the semiconductor film immediately afterdeposition is about 150 nm thick or higher, only the upper portion ofthe layer is melted during laser irradiation from above and the bottomportion of the layer retains amorphous regions. This adds to the thinfilm effect and the transistor properties deteriorate profoundly. Inother words, the maximum film thickness for the PECVD-crystallizationmethod is on the order of about 135 nm after crystallization.

[0072] (2-10, MOS Interface, the Gate Insulator Layer and the ThermalEnvironment)

[0073] With this invention, the gate insulator layer is formed using CVDor PVD after the semiconductor film crystallization is finished. Nomatter what process is used to form the gate insulator layer, it isdesirable that the insulator layer formation temperature be at 350° C.or lower. This is because it is important to prevent the thermaldegradation of the MOS interface and the gate insulator layer. This samething applies to all of the subsequent process steps. All of the processsteps after forming the gate insulator layer have to be held to 350° C.or less. In general, a gate insulator layer formed using CVD or PVD hasmany dangling bonds within the film; and the structure of the film isalso unstable. This invention terminates the dangling bonds by exposureto oxygen plasma. In addition, CVD silicon oxide films contain Si-OHgroups. Dangling bonds that have been terminated by such hydroxyl groupsand oxygen plasmas are unstable in heat, easily dissociating in anenvironment of 350° C. or higher. That is, dangling bonds such as Si-O-*and Si-* are generated again at the MOS interface and in the gateinsulator layer. These become interface states or fixed charges in theinsulator layer and cause a deterioration of the transistor properties.In the prior art, hydrogen plasma processing took place for an hour inorder to overcome this. In this invention, however, because all of theprocess steps after the semiconductor film has been formed take place at350° C. or less, such thermal degradation does not occur. For thisreason, hydrogenation is not required. With this invention, a highperformance, thin film semiconductor device can be produced easily andreliably. Although it is to be expected, the thermal degradation extendsto the underlevel protection layer as well. As described in section(2-1), thermal degradation of the underlevel protection layer will leadto the deterioration of the properties of the thin film semiconductordevice. Although it is not as sensitive as the gate insulator layer, theinfluence is such that it cannot be ignored. For this reason,optimization of the thin film semiconductor device is achieved,theoretically, by having all processing steps, including thesemiconductor film deposition steps, take place at a temperature, of350° C. or lower. Doing so will avoid thermal degradation of both theunderlevel protection layer and the gate insulator layer. Processes thatcan form semiconductor films at temperatures of 350° C. or lower includePECVD and sputtering.

[0074] (2-11. The VHS-PECVD Reactor Used in this Invention)

[0075] First of all, FIG. 2 will be used to describe the generalconfiguration of the VHS-plasma enhanced chemical vapor depositionreactor (VHS-PECVD reactor) used in this invention. The PECVD reactor isa capacitively-coupled type, and the plasma is generated betweenparallel plate electrodes using a 144 MHz VHS power supply. The topdrawing in FIG. 2 is an overall perspective of the reaction chamber asviewed from above, a drawing of cross section A-A′ is shown in thebottom of FIG. 2. Reaction chamber 201 is isolated from the outside byreaction vessel 202, which is in a reduced pressure condition of fromabout 5 mtorr to 5 torr during film formation. Inside of reaction vessel202, lower plate electrode 203 and upper plate electrode 204 are placedin mutually parallel positions. These two electrodes form the parallelplate electrodes. The space between these parallel plate electrodes isreaction chamber 201. This invention uses parallel plate electrodes withdimension of 410 mm×510 mm. Since the distance between the electrodes isvariable from 10 mm to 50 mm, the volume of reaction chamber 201 variesfrom 2091 cm³ to 10455 cm³, depending on the distance between theelectrodes. The distance between the parallel plate electrodes can beset freely between 10 mm and 50 mm, as stated above, by moving theposition of lower electrode 203 up and down. Moreover, when set to adesignated electrode distance, the deviation of the electrode distanceover the 410 mm×510 mm plate electrode surfaces is a mere 0.5 mm. As aresult, the deviation in the electrical field strength that appearsbetween the electrodes is 5.0% or less over the plate electrodesurfaces; and an extremely uniform plasma is generated within reactionchamber 201. Substrate 205 on which thin film deposition is to takeplace is placed on top of lower plate electrode 203 and 2 mm of thesubstrate edge is held down by shadow frame 206. Shadow frame 206 hasbeen omitted from the upper drawing of FIG. 2 to make the overalldrawing of the PECVD reactor easy to understand. Heater 207 is installedwithin lower plate electrode 203. The temperature of lower plateelectrode 203 can be adjusted as desired from 25° C. to 400° C. Exceptfor the peripheral 5 mm, the temperature distribution within lower plateelectrode 203 is within ±1,0° C. relative to the set-point temperature.Essentially, even if the size of substrate 205 were 400 mm×500 mm, thetemperature deviation within the substrate could be maintained to within2.0° C. For example, if a conventional glass substrate (such as CorningJapan's #7059, Nippon Electric Glass Co., Ltd.'s OA-2, or NH TechnoGlass's NA35) were used as substrate 205, shadow frame 206 would holdsubstrate 205 down to prevent it from deforming concavely by the heatfrom heater 207 as well as to prevent unnecessary thin films from beingformed on the edges and back surface of the substrate. The reaction gas,which is made up of source gases and additional gases as required, flowsthrough tube 208 and is introduced into upper plate electrode 204. Itthen flows between gas diffusion plates 209 located inside upper plateelectrode 204, and flows from the entire surface of the upper plateelectrode into reaction chamber 201 at a virtually uniform pressure. Iffilm formation is taking place, some of the reaction gas will be ionizedwhen it exits the upper plate electrode and cause a plasma to begenerated between the parallel plate electrodes. From a part to all ofthe reaction gas will participate in film formation. Residual reactiongas that has not participated in film formation and gases formed as aresult of the film forming chemical reaction will become discharge gasesand be discharged through exhaust port 210 which is in the top of theperipheral section of reaction vessel 202. The conductance of dischargeport 210 is sufficiently large compared to the conductance between theparallel plate electrodes. The desired value is one that is 100 times ormore of the conductance between the parallel plate electrodes. Inaddition, the conductance between the parallel plate electrodes is evensufficiently larger than the conductance of gas diffusion plate 209, andthat desired value is also 100 times or more of the conductance of gasdiffusion plate 209. Through such a configuration, reaction gas can flowinto the reaction chamber virtually uniformly from the entire surface ofthe large 410 mm×510 mm upper plate electrode; and, at the same time,discharge gas will be discharged in all directions from the reactionchamber in an even flow. The flow rates of the various reaction gases totube 208 will be adjusted to their designated values by mass flowcontrollers. In addition, the pressure within reaction vessel 202 willbe adjusted to the desired value by conductance valve 211, which islocated at the exit of the discharge port. A pumping system, such as aturbomolecular pump, is located on the exhaust side of conductance valve211. In this invention, an oil-free magnetic levitation typeturbomolecular pump is used as part of the pumping system, and thebackground vacuum within reaction vessels such as the reaction chamberis set to the 10⁻⁷ torr level. In FIG. 2, arrows are used to show thegeneral flow of the gas. Both reaction vessel 202 and lower plateelectrode 203 are at ground potential. These and upper plate electrode204 are electrically isolated by insulation link 212. When a plasma isgenerated, for example, 144 MHz VHS waves that are generated from VHSwave oscillation source 213 are amplified by amplifier 214, pass throughmatching circuit 215, and are applied to upper plate electrode 204.

[0076] As stated above, because the PECVD reactor used in this inventionhas very sophisticated intra-electrode interval control and uniform gasflow, it is a thin film formation reactor that is able to handle largesubstrates of 400 mm×500 mm in size. However, by merely adhering tothese basic concepts, it can easily handle further enlargements in thesubstrate. Actually, it is possible to produce a reactor that can handleeven larger substrates of 550 mm×650 mm. In addition, in this invention,a common 144 MHz VHS wave frequency was used. Of course, VHS waves usingother frequencies may also be used. For example, VHF waves from 100 MHzto 1 GHz may all be used. On the other hand, if the rf frequency is from10 MHz to several hundred MHz (VHF), it is possible to generate a plasmabetween the parallel plate electrodes. Therefore, frequencies such as27.12 MHz, 40.68 MHz, 54.24 MHz and 67.8 MHz, which are whole numbermultiples of the industrial rf frequency (13.56 MHz) may be used. Inother words, by changing VHS wave oscillator 213, amplifier 214, andmatching circuit 215 of the PECVD reactor used in this invention, aplasma using electromagnetic waves of a desired frequency can be easilygenerated. In general, in the case of an electromagnetic wave plasma, ifthe frequency is increased, the electron temperature within the plasmawill increase and radicals can be easily created. For this reason, aswill be explained later, even if the temperature of the substrate is aslow as approximately 340° C., the deposited film will already be in apolycrystalline silicon condition immediately after deposition. Thus,poly-Si TFTs can be easily fabricated even without specialcrystallization process steps.

[0077] (2-12, Semiconductor Film Formation and the Gases Used forFormation When Using VHS-PECVD and Microwave PECVD)

[0078] One of the characteristics of this invention is that a filmdeposited by VHS-PECVD or microwave PECVD is polycrystalline immediatelyafter deposition (an as-deposited film). It is extremely difficult tomake a polycrystalline as-deposited film using normal PECVD processing.Since the substrate temperature is less than 400° C., the mobility ofsource materials such as silane on the surface of the growing filmdecreases; and the selectivity of the source material for thepolycrystalline state as opposed to the amorphous state is lost. Thisinvention eliminates this deficiency in the PECVD method by dilutingsource materials using noble gas elements and by using a VHS plasma ormicrowave plasma, both of which are capable of raising the electrontemperature. To form a polycrystalline film in the as-deposited state,radicals and ions of the noble gas elements, such as helium (He), neon(Ne), and argon (Ar), are generated, without generating radicals andions of the source materials, and must carry energy to the surface ofthe substrate. Because radicals and ions of source materials cause vaporphase reactions or react the instant they arrive at the substratesurface, selectivity is lost, thereby preventing polycrystalline growth.For these reasons, the generation of such radicals and ions within aplasma must be avoided at all costs. The source materials are carried tothe surface of the growing film in an inactive state and become adsorbedthere. Subsequently, if energy for reaction is supplied, such as by adilute gas, a polycrystalline film will be formed in the as-depositedstate. Consequently, dilution of the source gas is desired, and thisgives rise to the necessity of selecting as the dilution gas a gas thatpromotes reaction of the source materials on the substrate surface. Itgoes without saying that the noble gas elements are composed ofindividual atoms, and, for this reason the ionization potential spectrumis very simple. For example, the monovalent ionization potential ofhelium is 24.587 eV, while the divalent ionization potential is only54.416 eV. Further, the monovalent ionization potential of neon is21.564 eV, while the divalent ionization potential is 40.962 eV. Themonovalent ionization potential of argon is 15.759 eV, while thedivalent ionization potential is 27.629 eV, and the trivalent ionizationpotential is 40.74 eV. Therefore, when a small amount of sourcematerials is diluted in helium and a plasma is generated, most of theionized helium will be 24.587 eV monovalent ions. When a small amount ofsource materials are diluted in neon and a plasma is generated, the neonwill be ionized into mainly monovalent ions of 21.564 eV. For argon,although both the monovalent ions and divalent ions are dominant, argonradicals and ions are effectively generated even when the sourcematerial is not diluted by a large amount of argon because theionization energy is relatively low. In contrast to this, there ishydrogen, widely used as a dilution gas in the prior art, in which morethan ten different ionization potentials exist between 15 eV and 18 eVfor the ionization potential of the hydrogen molecules. For this reason,in contrast to noble gas elements such as helium which form plasmascontaining one or two energies (laser light if referred to in terms oflight), molecular gases such as hydrogen form plasmas containing amixture of energies (white light if referred to in terms of light). Justas laser light will transport energy more effectively than white light,energy is transported to the substrate surface more effectively when thesource gas is diluted by a noble gas element. In addition to the noblegas elements of helium, neon and argon, krypton (Kr) and xenon (Xe) mayof course also be used as dilution materials during the deposition ofsemiconductor films. On the other hand, since VHS and microwave plasmashave high average electron temperatures within the plasma, the radicalgeneration efficiency can be increased at relatively low power. In otherwords, since high power is not necessary, these plasmas generate fewhigh energy ions, and resulting film damage is kept to a minimum.Further, a high radical generation efficiency also increases the filmgrowth rate. If this invention were also carried out using the 13.56 MHzrf plasma used widely in the prior art, the film formation rate would beextremely slow, less than several Å/min, making it absolutely unsuitablefor utilization. Moreover, a very slow film formation rate will beharmful, reducing the quality of the film. Which is to say that it isprecisely because VHS plasmas and microwave plasmas are used that thisinvention can be attained. In this sense, this invention can be veryeasily achieved by also using microwave PECVD, having a frequency aninteger multiple of 2.45 GHz. And with such systems, there is an evengreater degree of freedom in film formation conditions than inVHS-PECVD, meaning a semiconductor film with even better crystallinitycan be deposited with greater ease.

[0079] (2-13, Optimum Film Thicknesses for VHS-PECVD and Microwave PECVDAs-Deposited Films)

[0080] When placing a film in the polycrystalline state immediatelyafter deposition (as-deposited) using VHS-PECVD or microwave PECVD, thefilm quality for film thicknesses ranging from 0 to 500 Å will beextremely poor compared to normal crystallized films. The film willconsist of small, island-shaped crystalline grains in a sea of amorphousmaterial, have a very low degree of crystallinity, and contain a largenumber of defects. From 500 Å to 1000 Å, the ratio of crystal grains tothe amorphous material will increase. From about 1000 Å to 1500 Å, thesemiconductor surface will be generally covered with crystal grains; andthe amorphous components on the surface will almost disappear. Fromabout 1500 Å to 2000 Å, the size of the crystal grains will graduallyincrease along with the film thickness. At 2000 Å or higher, the filmwill grow while the crystal grains maintain approximately the sameshape. The film thickness dependency of the transistor properties willalso change in response to changes in the film quality relative to thefilm thickness. At 2000 Å or higher, because the film quality willexhibit virtually no change (because there is almost no thin filmdegradation), the thin film effect is active; and the thinner the film,the better the transistor properties become. At film thicknesses of 2000Å to 1500 Å, thin film degradation will begin to take effect. Yet, asbefore, the thin film effect will remain dominant. Although this will bemore lax than at 2000 Å or higher, even here, the thinner the film thebetter the transistor properties become. Between 1500 Å and 200 Å, thinfilm degradation and the thin film effect become competitive andtransistor properties in the on condition reach their maximum values.With a film thickness of less than 200 Å, thin film degradationovercomes the thin film effect, and the thinner the film, the poorer thetransistor properties. Put another way, in the case of this invention,transistor properties are the best at semiconductor film thicknessesfrom 200 Å to 1500 Å, but ideally between 400 Å to 1300 Å. Until thispoint, the discussion has been about transistor properties in the onstate; but the leak current will also vary with the thickness of thefilm. The principles of off state leakage in thin film semiconductordevice are not well understood. In this invention, the principles areunclear; but, if the film thickness is 1000 Å or more, there is a strongpositive correlation between the film thickness and off state leakage.The thicker the film, the larger the off state leakage. If the filmthickness is less than 1000 Å, the correlation weakens and becomesindependent of the off state leakage. In other words, between 0 and 1000Å, the off state leakage current is almost consistently at a minimum.Consequently, the on state transistor properties are best, and the filmthicknesses in which the off state leakage is the smallest are from 200Å to 1000 Å, but ideally from 400 Å to 1000 Å. When the thin filmsemiconductor device of this invention is used in an LCD, it isdesirable to consider the effects of light exposure on the off stateleakage current. Light exposure will cause an increase in the off stateleakage current in thin film semiconductor devices. This is called theoptical leakage current. Having a sufficiently small optical leakagecurrent is a condition for a good thin film semiconductor device. In thecase of the thin film semiconductor device of this invention, theoptical leakage current is proportional to the film thickness. From theperspective of reliable production and optical leakage currentcoexisting, it is desirable to have a film thickness from about 100 Å to800 Å. In a case in which the off state leakage and optical leakage areimportant, such as when using a thin film semiconductor device for thepixel switching element of an LCD, it is desirable to have asemiconductor film thickness from 100 Å to 700 Å. Moreover, when it isnecessary to give even stronger consideration to on current, the optimumthickness is from 200 Å to 800 Å. A system that would satisfy allconditions would have a thickness from 400 Å to 800 Å, but ideally from600 Å to 800 Å. Further, it is normally quite difficult to activateimplanted ions in the source and drain regions at a low temperature of350° C. or lower as happens with this invention. This is the reason thatto carry out activation in a stable manner, a lower limit must be setfor the semiconductor film thickness. With this invention, the desiredvalue is 300 Å or higher. If an LDD structure is to be utilized, athickness of 500 Å or higher is desired.

[0081] (2-14, Crystallization of the Semiconductor Film throughVHS-PECVD and Microwave PECVD)

[0082] As described in detail in section (2-12), although apolycrystalline film in the as-deposited state can be obtained easilyusing VHS-PECVD, the film quality is not as good as a crystallizationfilm. On the other hand, it is difficult to crystallize a film obtainedfrom the normal PECVD process as long as it has not been dehydrogenatedor carefully annealed. In contrast, a semiconductor film from VHS-PECVDor microwave PECVD can be very easily crystallized using RTA or VST-SPC,or be melt crystallized such as by laser irradiation. Since most of thefilm will already be in an as-deposited crystalline state and residualamorphous components will be limited, crystallization of residualamorphous components can be achieved by means of a relatively low energysupply. Also, even when melt crystallization progresses using highenergy, the polycrystalline components play the role of preventing theevaporation and scattering of semiconductor atoms. Thus, crystallizationcan proceed smoothly without semiconductor film damage, surfaceroughness, material loss and other problems. Ultimately, it can be saidthat rather than having a film obtained through the VHS-PECVD process orthe microwave PECVD process as the active area of a thin filmsemiconductor device in the as-deposited state, it is more suitable tohave such a film be the first semiconductor layer when producing lowtemperature poly-Si TFTs in which the highest temperature of the processstep is 350° C. or lower using melt crystallization. Put differently, ahigh-performance thin film semiconductor device can be produced byforming a semiconductor film on top of an insulating substance using theVHS-PECVD process or the microwave PECVD process and then crystallizingthis film using solid phase crystallization, such as RTA or VST-SPC, orcrystallizing it using melt crystallization, such as by laserirradiation, and then having the subsequent process steps take place at350° C. or lower.

[0083] Films deposited by VHS-PECVD or by microwave PECVD have qualitycloser to that of films deposited using LPCVD than to films deposited byPECVD. For this reason, the relationship between the transistorproperties and semiconductor film thickness obtained when producing athin film semiconductor device through crystallization becomesequivalent to the relationship possessed by a thin film semiconductordevice produced by the LPCVD process. In contrast to semiconductor filmsproduced by the LPCVD process, however, which show almost no reductionin film thickness before and after crystallization, some slightreduction can be found in VHS-PECVD and microwave PECVD films.Therefore, when crystallizing such films to produce thin filmsemiconductor devices, the discussion in section (2-6) can be applied asis by considering the semiconductor film thickness after crystallizationto be the same as the film thickness of a film from theLPCVD-crystallization method.

[0084] As discussed in the foregoing, using this invention, high-qualitysemiconductor films comprised of polycrystalline silicon films andothers can be easily formed at low temperatures of less than about 450°C. and 430° C. or lower. Thus, this invention greatly improves theproperties of thin film semiconductor devices as well as brings aboutreliable mass production. To be specific, it has the effects that aredescribed below.

[0085] Effect 1). Since the processing temperatures are below about 450°C., low-cost glass can be used and it is possible to lower the price ofthe products. Additionally, since it is possible to prevent the warpageof the glass under its own weight, it is easily possible to increase thesize of liquid crystal displays (LCDs).

[0086] Effect 2). Since the processing temperatures are approximately350° C. or less, there is no thermal degradation of the underlevelinsulator layer or gate insulator layer; and it is possible to easilyproduce high-performance thin film semiconductor devices with excellentreliability.

[0087] Effect 3). Laser irradiation can be applied uniformly over theentire substrate. The result of this is that the uniformity of each lotis improved, and reliable production has become possible.

[0088] Effect 4). The formation of self-aligned TFTs in which the gateelectrode is aligned with the source and drain by ion doping andsubsequent low temperature activation at approximately 300° C.-350° C.has become remarkably easy. As a result, it has become possible toreliably activate impurity ions. Additionally, it has become possible toeasily and reliably fabricate lightly doped drain (LDD) TFTs. BecauseLDD TFTs have been realized by low temperature process poly-Si TFTs, ithas become possible to decrease TFT element size and off leak currents.

[0089] Effect 5). In the prior art, only low temperature poly-Si TFTshaving SiO₂ made by ECR-PECVD showed good transistor characteristics.Using this invention, however, this has become possible usingconventional PECVD reactors. Consequently, practical gate insulatorlayer fabrication equipment applicable to large substrates and suitablefor mass production has been achieved.

[0090] Effect 6). Thin film semiconductor devices with higher oncurrents and lower off currents than those produced by the prior arthave been obtained. Additionally, the non-uniformity in these values hasbeen decreased.

[0091] Effect 7). When using low price, conventional glass, it hasbecome possible to form underlevel protection layers which effectivelyprevent the incorporation of impurities from the substrate into thesemiconductor film and simultaneously act as the underlevel protectionlayer for thin film semiconductor devices showing optimum electricalproperties. Also, the degradation of the electrical properties of thinfilm semiconductor devices as a result of stress from the underlevelprotection layer and the generation of cracks in the thin filmsemiconductor devices have been avoided.

[0092] Effect 8). The incorporation of constitutive elements such asfluorine (F) and carbon (C) from cleaning vapors into the semiconductorfilms when such films are formed by plasma enhanced chemical vapordeposition (PECVD) has been prevented. As a result, the amount ofimpurities among substrates can always be kept to a minimum and it hasbecome possible to reliably fabricate excellent thin film semiconductordevices.

[0093] Effect 9). Even when depositing semiconductor films by lowpressure chemical vapor deposition (LPCVD) at low temperatures less thanabout 450° C., it has become possible to simultaneously achieveuniformity, both within a single substrate and among differentsubstrates, and a suitable deposition rate. Therefore, it is possible toaccommodate increasing substrate size; and it has become possible tomass produce large-area LCDs.

[0094] Effect 10). Three types of variation in electrical properties ofthin film semiconductor devices are recognized: variation within asingle substrate, variation among substrates within the same lot, andvariation from lot to lot. Using this invention, however, all threetypes of variation can be controlled. The variation among lots processedby PECVD has been particularly significantly improved.

[0095] Effect 11). Even when the semiconductor film is grown by PECVD,good adhesion between the semiconductor film and the underlevelprotection layer can be achieved. In other words, problems such as thegeneration of numerous crater-shaped holes in the semiconductor film andpeeling of the films have been avoided.

[0096] Effect 12). Even without special crystallization processing,poly-Si TFTs can be fabricated reliably on large-area substrates by lowtemperature processing less than or equal to about 350° C.

BRIEF EXPLANATION OF THE FIGURES

[0097] FIGS. 1(a)-(d) are element cross-sectional views for each step inthe fabrication of a thin film semiconductor device showing onepractical example of this invention;

[0098]FIG. 2 shows the PECVD reactor used in this invention;

[0099]FIG. 3 shows the deposition chamber and the deposition chamberinterior of the LPCVD reactor of this invention;

[0100]FIG. 4 explains the substrate warpage resulting from a thermalenvironment; and

[0101]FIG. 5 explains the results of this invention.

THE BEST SYSTEMS FOR IMPLEMENTING THIS INVENTION

[0102] This invention is explained in further detail with reference tothe accompanying figures.

Example 1

[0103] FIGS. 1(a) through (d) show cross-sectional views of thefabrication process for a thin film MIS field effect transistor.

[0104] In Example 1, a 235 mm×235 mm sheet of non-alkaline glass (OA-2,manufactured by Nippon Electric Glass Co., Ltd.) was used for substrate101, though the type and size of the substrate are irrelevant for anysubstrate able to withstand the maximum processing temperature. First,silicon dioxide film (SiO₂ film) 102, which serves as the underlevelprotection layer, is formed on substrate 101 by means of atmosphericpressure chemical vapor deposition (APCVD), PECVD, sputtering or othermeans. In APCVD, the SiO₂ layer can be deposited using monosilane (SiH₄)and oxygen as source gases at a substrate temperature of between about250° C. and 450° C. In the PECVD and sputtering methods, the substratetemperature can be anywhere from room temperature to 400° C. In Example1, a 2000 Å SiO₂ film was deposited at 300° C. by APCVD using SiH₄ andO₂ as source gases.

[0105] Then, an intrinsic silicon layer, which later becomes the activelayer of the thin film semiconductor device, was deposited to athickness of approximately 500 Å. The intrinsic silicon layer wasdeposited over 58 minutes at a temperature of 425° C. by a high vacuumLPCVD reactor having a 200 sccm flow of disilane (Si₂H₆) as the sourcegas. The high vacuum LPCVD reactor used in Example 1 has a capacity of184.51. Seventeen substrates were inserted facedown in the reactionchamber, which was maintained at 250° C. After the substrates wereinserted, the turbomolecular pump was started. After the pump reachedsteady-state speed, a two-minute leak test was performed. The leak ratefrom outgassing and other sources at this time was 3.1×10⁻⁵ torr/min.The 250° C. insertion temperature was then-raised to a depositiontemperature of 425° C. over a period of 1 hour. For the first 10 minutesafter heating was initiated, no gas was introduced into the reactionchamber and heating was performed in a vacuum. The ultimate backgroundpressure reached in the reaction chamber 10 minutes after the onset ofheating was 5.2×10⁻⁷ torr. During the remaining 50 minutes of theheating period, nitrogen gas having a purity of at least 99.9999% wascontinuously introduced at the rate of 300 sccm. The equilibriumpressure in the reaction chamber at this time was 3.0×10⁻³ torr. Afterthe deposition temperature was reached, the source gases, Si₂H₆ and99.9999% pure helium (He) for dilution, were introduced at the flowrates of 200 sccm and 1000 sccm, respectively; and the silicon film wasdeposited over a period of 58 minutes. The pressure immediately afterSi₂H₆ and other gases were introduced into the reaction chamber was 767mtorr; and the pressure 57 minutes after these source gases wereintroduced was 951 mtorr. Silicon films obtained in this way were 501 Åthick; and, except for the 7 mm periphery of the substrate, thethickness of the film varied less than ±5 Å over the 221 mm×221 mmsquare region. In Example 1, the silicon layer was formed as describedby means of LPCVD, but PECVD and sputtering can also be used. In thePECVD and sputtering methods, silicon film deposition temperature may beset anywhere between room temperature and approximately 350° C.

[0106] Silicon films obtained in this manner are high-purity a-Si films.Next, this a-Si layer is crystallized by irradiating it for a shortperiod of time with either optical energy or electromagnetic energy,thereby changing it into polycrystalline silicon (poly-Si). In Example1, the a-Si layer was irradiated using a xenon chloride (XeCl) excimerlaser (wavelength of 308 nm). The laser pulse width at full-width, halfmaximum intensity was 45 ns. Since this irradiation time is extremelybrief, the substrate is not heated when the a-Si is crystallized intopoly-Si, hence substrate deformation does not occur. Laser irradiationwas performed in air with the-substrate at room temperature (25° C.). An8 mm×8 mm square area is irradiated during each laser irradiation, andthe irradiated area is shifted by 4 mm after each irradiation. At first,scanning is performed in the horizontal direction (Y direction), andthen the substrate is then shifted 4 mm in the vertical direction (Xdirection). It is then moved 4 mm more in the horizontal direction,where it is again scanned. Thereafter these scans are repeated until theentire surface of the substrate has been subjected to the first laserirradiation. The energy density of this first laser irradiation was 160mJ/cm². After the first laser irradiation was completed, a second laserirradiation was performed over the entire surface at an energy densityof 275 mJ/cm². The scanning method used for the second irradiation isidentical to that used for the first laser irradiation; scanning isperformed while shifting the 8 mm×8 mm square irradiation area in 4 mmincrements in the Y and X directions. This two-stage laser irradiationprovides the means for uniformly crystallizing the a-Si to form poly-Siover the entire substrate. While an XeCl excimer laser was used as theoptical energy or electromagnetic energy in Example 1, other energysources may be used provided the energy irradiation time is less thanseveral tens of seconds. For example, irradiation may also be performedusing an ArF excimer laser, XeF excimer laser, KrF excimer laser, YAGlaser, carbon dioxide gas laser, Ar laser, dye laser or other laser, aswell as by an arc lamp, tungsten lamp or other light source. When usingan arc lamp to irradiate the a-Si layer to transform it into poly-Si,output of about 1 kW/cm² or greater and an irradiation time of about 45seconds is used. Even at the time of this crystallization, the energyirradiation time is short, so problems such as deformation and crackingcaused by heating the substrate do not occur. This silicon film was thenpatterned and channel region semiconductor film 103, which becomes theactive layer of the transistor, was created. See FIG. 1(a).

[0107] Next, gate insulator layer 104 is formed by means of ECR-PECVD,PECVD, or other deposition method. In Example 1, a SiO₂ film was used asthe gate insulator layer and was deposited to a thickness of 1200 Åusing PECVD. See FIG. 1(b). Immediately prior to setting the substratein the PECVD reactor, the substrate was soaked for 20 seconds in a 1.67%dilute hydrofluoric acid solution to remove the native oxide layer fromthe surface of the semiconductor film. There was an interval ofapproximately 15 minutes from the time the oxide layer was removed untilthe time the substrate was loaded in the loadlock chamber of the PECVDreactor. This time interval should be as short as possible in order topreserve MOS interface cleanliness; an interval of about 30 minutes, atmost, is desirable. In the PECVD method, monosilane (SiH₄) and nitrousoxide (N₂O) were used as source gases to form the gate insulator layerat a substrate temperature of 300° C. A 900 W rf plasma at 13.56 MHz wasgenerated at a pressure of 1.5 torr. The SiH₄flow rate was 250 sccm andthe N₂O flow rate was 7000 sccm. The SiO₂ deposition rate was 48.3 Å/s.Immediately before and after the SiO₂ layer was formed under theseconditions, the silicon layer and deposited oxide layer were exposed toan oxygen plasma to improve the MOS interface and the oxide film. Whilemonosilane and nitrous oxide were used as source gases in Example 1, anorganic silane, such as TEOS (Si—(O—CH₂—CH₃)₄), and an oxidizing gas,such as oxygen, could also be used. In addition, although ageneral-purpose PECVD reactor was used here, naturally, ECR-PECVD couldalso be used to form the insulator layer. Regardless of the type of CVDreactor or source gases used, it is desirable that the insulator layerformation temperature be 350° C. or less. This is important forpreventing thermal degradation of the MOS interface and gate insulatorlayer. The same thing applies to all processes described below. Allprocess temperatures after gate insulator layer deposition must be keptto 350° C. or less. Controlling the process temperature in this wayenables high-performance thin film semiconductor devices to befabricated easily and reliably.

[0108] Next, a thin film, which becomes gate electrode 105, is depositedby such means as sputtering, evaporation, or CVD. In Example 1, tantalum(Ta) was selected as the gate electrode material and was deposited to athickness of 5000 Å by means of sputtering. The substrate temperatureduring sputtering was 180° C., and argon (Ar) containing 6.7% nitrogen(N₂) was used as the sputtering gas. The optimum nitrogen concentrationin the argon is from 5.0% to 8.5%. The tantalum film obtained underthese conditions is mostly α-Ta with a resistivity of 40 μΩcm.Therefore, the sheet resistivity of the gate electrode in Example 1 is0.8 μ/square.

[0109] Patterning is carried out after the thin film which becomes thegate electrode is deposited. Then impurity ions 106 such as phosphorouswere implanted using a bucket-type non-mass-separating ion dopingapparatus (ion doping) to form source and drain regions 107 and channelregion 108 in the intrinsic silicon layer. See FIG. 1 (c). In Example 1,the objective was to fabricate NMOS TFTs, so implantation was carriedout to 5×10¹⁶ 1/cm² using hydrogen-diluted 5% phosphine (PH₃) source gasat a high frequency power of 38 W and an acceleration voltage of 80 kV.A suitable value ranging from about 20 W to 150 W was used for the highfrequency power. During PMOS TFT fabrication, implantation was carriedout to about 5×10¹⁵ 1/cm² using a hydrogen-diluted 5% diborane (B₂H₆)source gas, a high frequency power of between 20 W to 150 W, and anacceleration voltage of 60 kV. When fabricating CMOS TFTs, the NMOS andPMOS are alternately covered with a mask of suitable material, such aspolyimide resin; and ions are implanted into each using the methoddescribed above.

[0110] Next, interlevel insulator layer 109 was deposited to 5000 Å. InExample 1, the interlevel insulator layer was formed by PECVD usingSiO₂. In the PECVD method, the interlevel insulator layer was formed ata substrate temperature of 300° C. using TEOS (Si—(O—CH₂—CH₃)₄) andoxygen (O₂) as source gases. An 800 W rf plasma at 13.56 MHz wasgenerated at a pressure of 8.0 torr. The TEOS flow rate was 200 sccm,and the O₂ flow rate was 8000 sccm. The deposition rate for the Si0 ₂film at this time was 120 Å/s. After ions were implanted and theinterlevel insulator layer was formed, thermal annealing was performedfor 1 hour at 300° C. in an oxygen atmosphere to achieve activation ofimplanted ions and densification of the interlevel insulator layer. Thedesired temperature of this thermal annealing is between 300° C. and350° C. Contact holes are opened after thermal annealing is performed,and source and drain electrodes 110 are formed by sputtering or othermeans to complete the thin film semiconductor device. See FIG. 1(d).Indium tin oxide (ITO) and aluminum. (Al) and the like are used forsource and drain electrodes. The temperature of the substrate duringsputtering of these conductors is in the approximate range of 100° C. to250° C.

[0111] The transistor characteristics of the thin film semiconductordevices that were experimentally fabricated in this way were measured.It was found that I_(ON)=(23.3 +1.73, −1.51)×10⁻⁶ A at a 95% confidencelevel. Here, the on current, I_(ON), is defined as the source-draincurrent Ids when transistors are turned on at source-drain voltage ofVds=4 V and gate voltage of Vgs=10 V. The off current when thetransistor was turned off at Vds=4 V and Vgs=0 V was I_(OFF)=(1.16+0.38,−0.29)×10⁻¹² A. These measurements were taken at a temperature of 25° C.for transistors having channel length L=10 μm and width W=10 μm. Theeffective electron mobility (J. Levinson et al. J. Appl. Phys. 53, 1193′82) found from the saturation current region was μ=50.92±3.26 cm²/v.sec.Conventional low temperature process poly-Si TFTs haveI_(ON)=(18.7+2.24, −2.09)×10⁻⁶ A, and I_(OFF)= (4.85+3.88, −3.27)×10⁻¹²A. As described, this invention achieves for the first time, by means ofa low temperature process in which a maximum processing temperature of425° C. or less is maintained for no more than several hours, extremelygood and uniform thin film semiconductor devices that have highmobility, low variation, and Ids that changes seven orders of magnitudeor more for a gate voltage change of 10 V. As described previously, theuniformity of laser crystallization, whether within a single substrateor from lot to lot, has been a serious problem. This invention, however,greatly reduces variation of both on current and off current. Theimprovement over existing technologies in off current uniformity isparticularly marked; and when thin film semiconductor devices fabricatedas described by this invention are applied to LCDs, a uniform,high-quality picture is obtained over the entire LCD screen. Moreover,improved uniformity means that the initial silicon film is stable withrespect to variations in the laser source; thus, this invention alsoeffects conspicuous improvement with respect to variations amongproduction lots. As described, this invention achieves extremelyreliable crystallization of silicon through the use of energyirradiation, such as laser irradiation. Tests performed by the inventorverified that when the initial silicon layer was formed at lowtemperature of less than 450° C. and at a silicon layer deposition rateof more than approximately 2 Å/min, the silicon layer was stable withrespect to variations of the laser and, moreover, that thin filmsemiconductor devices having good transistor properties are fabricatedeven when a SiO₂ layer not formed by ECR-PECVD is used as the gateinsulator layer. In addition, poly-Si layers obtained by this method arealso stable with respect to lightly doped drain (LDD) structureformation by means of ion doping, as is described later, and are easilyactivated. This is indirectly related to the fact that a-Si layersformed under these conditions are perfectly amorphous withoutmicrocrystalline grains, and that the components that make up the a-Silayer are made of large regions. Because the a-Si layer does not containmicrocrystallites, the crystallization that accompanies energyirradiation progresses uniformly within the irradiated region. At thesame time, because the a-Si layer is composed of large regions, the sizeof the grains after crystallization is large and high-performanceelectrical characteristics can be obtained. In other words, ideal a-Sifilms can be obtained by optimizing the deposition conditions for theinitial a-Si layer; and uniform, high-quality poly-Si films can beobtained by crystallizing this initial a-Si layer. Amorphous siliconfilms formed using technology of the prior art suffered from theproblems described above, as no heed was paid to the quality of the a-Silayer; for example, deposition temperature in the LPCVD process wasabout 550° C., and substrate temperature in the PECVD method was in theneighborhood of 400° C. One more important point of this invention isthat the process temperature after poly-Si film formation is held to350° C. or less. By controlling the temperature in this way, MOSinterface and insulator layer quality can be stabilized. In this sense,this invention, as shown in FIG. 1, is especially useful for top-gateTFTs. In the case of bottom-gate TFTs, the silicon layer is depositedafter the gate insulator layer has been formed and, moreover, is latersubjected to crystallization by laser irradiation or other means.Therefore, part of the MOS interface and gate insulator layer is, ofnecessity, exposed, albeit for a brief time, to a high-temperaturethermal environment of nearly 1000° C. This thermal environment not onlyroughens the MOS interface but also alters the chemical composition andchemical bonds of the insulator layer in the vicinity of the MOSinterface, thus causing transistor characteristics to deteriorate andtriggering the problem of increased non-uniformity.

Example 2

[0112] Other examples of implementations of this invention will also beexplained using FIGS. 1(a) through (d).

[0113] In Example 2, sheets of non-alkaline glass (OA-2manufactured byNippon Electric Glass Co., Ltd.) measuring 300 mm×300 mm andcrystallized glass (TRC-5 manufactured by Ohara) measuring 300 mm×300 mmwere used for substrate 101. The strain point of OA-2 is approximately650° C. TRC-5, on the other hand, is a crystallized glass, so the strainpoint cannot be defined. Since absolutely no substrate deformation orwarpage can be detected up to a temperature of about 700° C., however,the strain point of TRC-5 can, in practice, be said to be above about700° C. First, silicon oxide film 102, which becomes the underlevelprotection layer, was deposited by PECVD onto substrate 101. The siliconoxide film was deposited under the same conditions that the gateinsulator layer was deposited in Example 1. The thickness of the siliconoxide film was 300 nm, and the center line mean surface roughness was0.98 nm. As with the gate insulator layer in Example 1, the underlevelprotection layer surface was exposed to an oxygen plasma for 15 secondsboth immediately before and immediately after oxide film deposition.

[0114] An intrinsic silicon layer, which later becomes the active layerof the thin film semiconductor device, was then deposited toapproximately 500 Å. Just as in Example 1, the intrinsic silicon layerwas deposited by the high vacuum LPCVD reactor described in section(2-3). The source gas, disilane (Si₂H), was introduced at a flow rate of400 sccm; and deposition occurred at a temperature of 425° C. and apressure of 320 mtorr. The deposition rate was 1.30 nm/min. Thirty-fiveOA-2 substrates and 35 TRC-5 substrates were placed in the depositionchamber, which was maintained at 250° C. Each OA-2 substrate was pairedback-to-back with a TRC-5 substrate. The TRC-5 substrates were placedfacedown and the OA-2 substrates were placed faceup on top of the TRC-5substrates. There was a 10 mm space between substrate pairs. The area ofthe region in the deposition chamber over which the semiconductor filmwas deposited was 88262 cm², and the disilane flow rate per unit areawas 4.53×10⁻³ sccm/cm². After the substrates were placed in the chamber,the chamber was heated over a period of one hour from the 250° C.insertion temperature to the 425° C. deposition temperature; and, afterthermal equilibrium was achieved at 425° C., the silicon layer wasdeposited over 40 minutes. The pressure during film deposition wasmaintained at 320 mtorr by the LPCVD reactor's pressure control unit.The thickness of the silicon films deposited in this manner was 52.4 nm.

[0115] Next, these a-Si films were exposed briefly to optical energy orelectromagnetic energy to melt crystallize the a-Si and transform itinto polysilicon (poly-Si). A xenon chloride (XeCl) excimer laser(wavelength of 308 nm) was also used in Example 2. The substrates weresoaked for 20 seconds in a solution of 1.67% hydrofluoric acidimmediately prior to laser irradiation to remove the native oxide layerfrom the surface of the semiconductor layer. There was a time intervalof approximately 20 minutes after the oxide layer was removed and beforelaser irradiation. After the semiconductor layer was crystallized,poly-Si TFTs were fabricated by the low temperature process usingexactly the same process as described in Example 1.

[0116] The transistor characteristics of the thin semiconductor devicesexperimentally fabricated in this way were measured. It was found thaton current was I_(ON)=(41.9+2.60, −2.25)×10⁻⁶ A at a 95% confidencelevel. Off current was I_(OFF)=(6.44+2.11, −1.16)×10⁻¹³ A. Themeasurement conditions here were the same as the conditions inExample 1. Effective electron mobility was μ=90.13±4.61 cm²/v.sec.Extremely good thin film semiconductor devices were fabricated reliablyusing a simple process.

Example 3

[0117] After forming the poly-Si-layer using the method described indetail in Example 1, an SiO₂ layer corresponding to the gate insulatorlayer described in detail in Example 1 was deposited without patterningthis poly-Si layer, and impurity ions such as PH₃ were implanted in thepoly-Si layer by ion doping, details of which were explained inExample 1. The thicknesses of the poly-Si layer and Sio₂ layer and theconditions under which they were deposited were exactly the same as theywere in Example 1. Impurity ion implantation conditions were also thesame as those described in Example 1 except that the implantation dosewas 3×10¹³ cm⁻². Example 3 corresponds to the formation of the LDDregion in TFTs explained in Example 1. After phosphorous ions wereimplanted, thermal annealing was performed at 300° C. in oxygen for onehour, again just as in Example 1. After that the insulator layer wasstripped off and the sheet resistance of the n-type poly-Si layer thatcontained phosphorous ions was measured. Sheet resistance of a 221mm×221 mm square region excluding the 7 mm periphery of the substratewas (14±_(—)2.6) kΩ/square at a confidence level of 95%. In the priorart, as reported on page 437 of SSDM '93 (solid state Devices andMaterials 1993), activation was not possible without adding a specialprocess such as hydrogen implantation. Moreover, the sheet resistancevalue at that time was high, 50 kΩ or more, and its variation was 10 kΩor more. In contrast, this invention allows a low-resistance LDD regionto be simply formed using ion doping and makes it possible to achieveresistance variation of no more than one-quarter that of the past.

Example 4

[0118] In Example 4, the underlevel protection layer and semiconductorlayer were formed sequentially by means of PECVD using 13.56 MHz rfwaves. Crystallization was then performed to fabricate the thin filmsemiconductor device.

[0119] Substrate 101 was a 360 mm×465 mm×0.7 mm sheet of non-alkalineglass. Prior to placement of the glass substrate in the PECVD reactor,the thin film that formed in the deposition chamber during deposition ofthe thin film on the previous substrate is removed from the depositionchamber. In other words, the deposition chamber is cleaned for 15seconds. The cleaning conditions were rf power of 1600 W (0.8 W/cm²),electrode separation distance of 40 mm, NF₃ flow rate of 3200 sccm,argon flow rate of 800 sccm, and pressure of 1.0 torr. Next, after avacuum is pulled for 15 seconds, a silicon nitride layer, which servesas the passivation layer, is deposited for 15 seconds in the depositionchamber. The deposition conditions were rf power of 300 W (0.15 W/cm²),electrode separation distance of 40, pressure of 1.2 torr, nitrogen flowrate of 3500 sccm, ammonia flow rate of 500 sccm, and monosilane flowrate of 100 sccm. After a vacuum is pulled for 15 seconds, the substrateis placed in the deposition chamber. It takes approximately 10 secondsfor the substrates that are set up in the loadlock chamber to bepositioned in the deposition chamber. A stabilization period of 30seconds is allowed before the next underlevel protection layer isdeposited. All process parameters for the stabilization period areidentical to the deposition conditions for the underlevel protectionlayer, except that plasma is not generated. The lower plate electrodetemperature, from the underlevel protection layer to the depositedsemiconductor film, is 360° C.; and the substrate surface temperature isapproximately 340° C. After the stabilization period expires, theunderlevel protection layer is deposited. The underlevel protectionlayer consists of a deposited layer of silicon nitride and a layer ofsilicon oxide. First, the silicon nitride layer is deposited over 30seconds at rf power of 800 W, electrode separation distance of 25 mm,pressure of 1.2 torr, nitrogen flow rate of 3500 sccm, ammonia flow rateof 500 sccm, and monosilane flow rate of 100 sccm. The silicon oxidelayer is then deposited for 30 seconds at rf power of 900 W, electrodeseparate distance of 25 mm, pressure of 1.5 torr, monosilane flow rateof 250 sccm, and N₂O flow rate of 7000 sccm. The nitride and oxidelayers are each approximately 150 nm thick, forming an underlevelprotection layer about 300 nm thick. After formation, the oxide layer isexposed to an oxygen plasma for 20 seconds. Oxygen plasma was irradiatedat rf wave power of 900 W (0.45 W/cm²), electrode separation distance of12 mm, pressure of 0.65 torr, and oxygen flow rate of 3000 sccm. After avacuum is pulled for 15 seconds, the oxide layer is exposed to hydrogenplasma for 20 seconds. The hydrogen plasma conditions were rf power of100 W (0.05 W/cm²), electrode separation distance of 25 mm, pressure of0.5 torr, and hydrogen flow rate of 1400 sccm. Upon completion ofhydrogen plasma irradiation, the semiconductor layer is deposited over60 seconds. The deposition conditions were rf power of 600 W (0.3W/cm²), electrode separation distance of 35 mm, pressure of 1.5 torr,argon flow rate of 14 SLM, and monosilane flow rate of 200 sccm. Thisdeposits an amorphous silicon film approximately 50 nm thick. Afterdeposition of the semiconductor layer a vacuum is pulled for 15 seconds,and the amorphous silicon film is exposed to hydrogen plasma for 20seconds. The hydrogen plasma is generated under the same conditions asthe hydrogen plasma that was generated prior to semiconductor layerdeposition. Next, after a vacuum is pulled for 15 seconds, the amorphoussilicon film is exposed to oxygen plasma for 20 seconds. The conditionsunder which oxygen plasma is generated are the same as those under whichthe oxygen plasma was generated after underlevel protection layerformation except for the fact that the distance between electrodes is 45mm. Finally, after a vacuum is pulled for 15 seconds, the substrates areremoved from the deposition chamber in about 10 seconds. With thisprocess, tact time is 6 minutes and 10 seconds, making it possible tosequentially deposit the underlevel protection layer and thesemiconductor layer. After this, thin film semiconductor devices werefabricated using the exact same process as was described in Example 2.

[0120] The transistor characteristics of thin film semiconductors thatwere experimentally fabricated in this way were measured. It was foundthat on current was I_(ON)=(19.6+1.54, −1.49)×10⁻⁶ A at a 95% confidencelevel, and that off current was I_(OFF)=7.23+2.76, −2.72)×10⁻¹³ A.Effective electron mobility was μ=36.83_(—)} 2.35 cm²/v.sec. Themeasurement conditions correspond to those described in Example 1.

Example 5

[0121] Next, a low temperature process (350° C. or less) for depositing,using the PECVD reactor that was explained in section (2-11),crystalline semiconductor films that do not require crystallization bylaser irradiation or other irradiation means; the method of fabricatingthin film semiconductor devices using this method; and thecharacteristics of these films will be described in detail. Thesubstrates are prepared by the method described in section (2-1).Although the semiconductor layers and source gases described in section(2-2) are all applicable, silicon film is discussed here as an exampleand monosilane (SiH₄) is used as the source gas.

[0122] In Example 5, substrate 101 was a 360 mm×465 mm×1.1 mm sheet ofnon-alkaline glass (OA-2 , manufactured by Nippon Electric Glass Co.,Ltd.), and the SiO₂ layer of the underlevel protection layer wasdeposited to a thickness of 2000 Å by means of APCVD using SiH₄ and O₂as source gases. The substrate temperature was 300° C..

[0123] Then, an approximately 750 Å intrinsic silicon layer, whichbecomes the active layer of the thin film semiconductor device, wasdeposited. The intrinsic silicon layer was deposited by means of aVHS-PECVD reactor, described previously in section (2-11), using a 50sccm flow rate of monosilane (SiH₄) as the source gas and a 4800 sccmflow rate of argon (Ar), one of the noble gas elements, as a dilutiongas. During deposition of the intrinsic silicon layer, the VHS wavepower was 715 W, the pressure in the reactor chamber was 0.8 torr, thedistance between parallel plate electrodes was 35.0 mm, the lower plateelectrode temperature was 400° C., and the substrate surface temperaturewas 340° C. The semiconductor layer obtained in this way is a siliconlayer of high purity and is polycrystalline in the state immediatelyafter deposition (“as-deposited”). The degree of crystallinity wasmeasured using multiple wavelength spectroscopic ellipsometry and wasfound to be 78%. Usually, if the degree of crystallinity found by meansof spectroscopic ellipsometry is less than 30%, the silicon layer isconsidered to be amorphous; if it is 70% or more, the layer isconsidered to be polycrystalline; and if it is between 30% and 70%, itis considered to be mixed. Hence, the film that was obtained was clearlypolycrystalline in the as-deposited state. In fact, a sharp Raman shiftwas detected by means of Raman spectroscopy in the wave number region inthe vicinity of 520 cm⁻¹, which indicates a crystalline state; inaddition, it was observed by means of X-ray diffraction that thecrystals have a relatively strong preferred orientation in the {220}direction.

[0124] Next, this silicon layer was patterned and channel areasemiconductor layer 103, which becomes the active layer of thetransistor, was formed, see FIG. 1(a). Using exactly the same processesas those that were used to fabricate the thin film semiconductor devicethat was explained in detail in Example 1, the gate insulator layer wasformed, see FIG. 1(b), the gate electrode was formed, the source anddrain regions and channel were formed by ion implantation, see FIG.1(c), the interlevel insulator layer was formed, implanted ions wereactivated and the interlevel insulation layer was densified by thermalannealing, contact holes were opened, source and drain electrodes wereformed, and the thin film semiconductor device was then completed, seeFIG. 1(d). In Example 5, therefore, the maximum processing temperatureafter the first process, that of semiconductor layer formation, was 300°C. The temperature of the process for forming the gate insulator layerand the temperature of the thermal annealing process for implanted ionactivation and interlevel insulator layer densification must not exceeda maximum temperature of 350° C. In other words, as detailed in section(2-10 ), to uniformly and reliably fabricate excellent thin filmsemiconductor devices over large areas, the maximum process temperatureafter the first process, that of semiconductor layer formation, must notexceed 350° C.

[0125] The transistor characteristics of the thin film semiconductordevices that were experimentally fabricated in this way were measured.It was found that I_(ON)=(1.22±0.11, −0.10)×_(—)10⁻⁶ A at a 95%confidence level. Here, the on current, I_(ON), is defined as thesource-drain current Ids when transistors are turned on at source-drainvoltage of Vds=4 V and gate voltage of Vgs=10 V. The off current whenthe transistor was turned off at Vds=4 V and Vgs=0 V wasI_(OFF)=(1.18+0.35, −0.30)×10⁻¹³ A. The measurements were taken at atemperature of 25° C. for transistors having channel length L=10 μm andwidth W=10 μm. The effective electron mobility (J. Levinson et al. J.Appl. Phys. 53, 1193'82) found from the saturation current region wasμ=3.41±0.22 cm²/v.sec.

[0126] The maximum process temperature reached in Example 5 was the 400°C. lower plate electrode temperature during deposition of thesemiconductor layer by means of a VHS-PECVD reactor; the substratesurface temperature at that time was 340° C.. As shown by this example,pol.y-Si TFTs, which are a kind of crystalline thin film semiconductordevice, were successfully fabricated at extremely low processtemperature using a simple manufacturing method that does not requirecrystallization by laser irradiation or other means. While values for oncurrent and mobility are far from those in Example 1, in which laserirradiation was employed, they are from 4 to nearly 10 times higher thanthe values for a-Si TFTs fabricated by conventional methods with amaximum processing temperature of 400° C.. Additionally, source anddrain regions in Example 5 were formed by means of ion implantation withthe gate electrode used as a mask. Moreover, because implanted ions wereactivated at low temperatures of from 300° C. to 350° C., implanted ionsfrom the source and drain regions essentially do not diffuse at all intothe channel region. Therefore, the overlapping of gate electrodes andsource and drain regions is determined by horizontal projectiondeviation during ion implantation, and the deviation value is not morethan several hundred Å. In other words, the edges of the gate electrodeand the edges of the source and drain matched extremely closely in aso-called self-aligned structure. For that reason, the parasiticcapacitance between source and gate and between drain and gate isextremely small in comparison with that of a-Si TFTs. Due to these twofacts, when the thin film semiconductor devices of this invention areused as pixel switching elements for an active-matrix liquid crystaldisplay device (LCD), high-definition LCDs (LCDs having a large numberof picture elements), bright LCDs (LCDs having a high aperture ratio inwhich storage capacitors have been reduced or eliminated), andhighly-integrated LCDs (LCDs having a large number of picture elementsper unit area), all of which were heretofore impossible using a-Si TFTsof the prior art, can easily be achieved.

Example 6

[0127] Next, a low temperature process, having a maximum temperature ofabout 350° C. in which a microwave PECVD reactor is used to depositcrystalline semiconductor films that do not require crystallization bymeans of laser irradiation or other means, a method for fabricating thinfilm semiconductor devices using that method, and the characteristics ofthese thin film semiconductor devices will be described in detail. Thesubstrate is prepared using the method described in section (2-1). Thesemiconductor film and source gases described in section (2-2) can allbe applied, but here, for illustrative purposes, silicon film is usedand monosilane (SiH₄) is used as the source gas.

[0128] In Example 6, a 300 mm×300 mm x 1.1 mm sheet of non-alkalineglass (OA-2, manufactured by Nippon Efectric Glass Co., Ltd.) was usedfor substrate 101, and the underlevel protection layer and semiconductorlayer were deposited sequentially at a substrate temperature of 100° C.by means of ECR-PECVD reactor, a type of microwave PECVD reactor. Themicrowaves used were 2.45 GHz. The silicon oxide layer, which is theunderlevel protection layer, was deposited to 200 nm using SiH₄ and O₂as source gases. The underlevel protection layer was deposited using anoxygen flow rate of 100 sccm, silane flow rate of 60 sccm, microwavepower of 2250 w, reactor chamber pressure of 2.35 mtorr, and adeposition rate of 8.0 nm/s. After formation of the silicon oxide layer,the flow of silane to the deposition chamber was shut off and thesilicon oxide layer was exposed to an oxygen plasma for 10 seconds. Thepressure during oxygen plasma irradiation was 1.85 mtorr. Then, after avacuum was pulled for 10 seconds, the underlevel protection layer wasexposed to a hydrogen plasma using a hydrogen flow rate of 100 sccm,microwave power of 2000 W, and reaction chamber pressure of 1.97 mtorr.Next, without breaking the vacuum, an intrinsic silicon layer, whichbecomes the active layer of the thin film semiconductor device, wassuccessively deposited to about 75 nm. The intrinsic silicon layer wasdeposited by introducing monosilane (SiH₄), the source gas, at the rateof 25 sccm and argon (Ar), an element in the noble gas family, as adilution gas at the rate of 825 sccm. The film deposition conditionswere microwave power of 2250 W, reaction chamber pressure of 13.0 mtorr,and deposition rate of 2.5 nm/s. After deposition, the semiconductorlayer was again exposed in succession to a hydrogen plasma and an oxygenplasma for the purpose of protecting the surface of the semiconductorlayer and terminating dangling bonds in the semiconductor layer. Theconditions under which the hydrogen plasma and oxygen plasma weregenerated were identical to those used for the underlevel protectionlayer. The semiconductor film obtained in this way is a high puritysilicon layer and is polycrystalline in the state immediately afterdeposition (the as-deposited state). The degree of crystallinity wasmeasured using multiple wavelength spectroscopic ellipsometry and wasfound to be 85%.

[0129] Next, this silicon layer was patterned and channel regionsemiconductor film 103, which becomes the active layer of thetransistor, was formed. See FIG. 1(a). Using exactly the same processesas those that were used to fabricate the thin film semiconductor devicethat was explained in detail in Example 1, the gate insulator layer wasformed, see FIG. 1(b), the gate electrode was formed, the source anddrain regions and channel were formed by ion implantation, see FIG.1(c), the interlevel insulator layer was formed, implanted ions wereactivated and the interlevel insulator layer was densified by thermalannealing, contact holes were opened, source and drain electrodes wereformed, and the thin film semiconductor device was then completed, seeFIG. 1(d). In Example 6, therefore, the maximum processing temperaturethroughout all processing steps was 300° C..

[0130] The transistor characteristics of the thin film semiconductordevices that were experimentally fabricated in this way were measured.It was found, with a 95% confidence level, that on current wasI_(ON)=(1.71±0.13,−0.12)×_(—)10⁻⁶ A and off current wasI_(OFF)=(1.07+0.33, −0.28) ×10⁻¹³ A. Effective electron mobility wasμ=4.68 ±0.20 cm²/v.sec. Measurement conditions conform to those inExample 1. Using this invention, poly-Si TFTs can be fabricated by aprocess in which all process temperatures are 300° C. or less andwithout even introducing a special crystallization step.

Example 7

[0131] In this example, a semiconductor film obtained by VHS-PECVD wasexposed to laser irradiation to achieve melt crystallization and createa thin film semiconductor device. The fabrication process was the sameas that described in Example 5 except that the laser irradiation processwas added immediately after the semiconductor film was deposited. Thelaser irradiation method used was the same as that described in Example1, with the energy density of the first laser exposure changed to 130mJ/cm², and the energy density of the second laser exposure changed to240 mJ/cm².

[0132] The transistor characteristics of the thin film semiconductordevices that were experimentally fabricated in this way were measured.It was found, with a 95% confidence level, that on current wasI_(ON)=(22.4+1.70, −1.55)×10⁻⁶ A and off current wasI_(OFF)=(1.27+0.30,−0.26)×10⁻¹² A. Effective electron mobility wasμ=47.95±3.13 cm²/v.sec. Measurement conditions conform to those inExample 1.

Example 8

[0133] In this example a semiconductor film obtained by microwave-PECVDwas exposed to laser irradiation to achieve melt crystallization andcreate a thin film semiconductor device. The fabrication process was thesame as that described in Example 6 except that a laser irradiationprocess was added immediately after the semiconductor film wasdeposited. The laser irradiation method used was the same as thatdescribed in Example 1, with the energy density of the first laserexposure changed to 150 mj/cm² and the energy density of the secondlaser irradiation exposure changed to 270 mJ/cm².

[0134] The transistor characteristics of the thin film semiconductordevices that were experimentally fabricated in this way were measured.It was found, with a 95% confidence level, that on current wasI_(ON)=(39.8+2.45,−1.57)×10⁻⁶ A and off current wasI_(OFF)=(5.80+2.09,−1.26 ) Effective electron mobility was μ=85.63±4.38cm²/v.sec. Measurement conditions conform to those in Example 1.

Example 9

[0135] Active matrix substrates using each of the thin filmsemiconductor devices obtained by the methods described in the aboveexamples as pixel TFTs and driver circuit TFTs were manufactured. Liquidcrystal panels were produced using some of these active matrixsubstrates. Liquid crystal display device modules were manufactured byequipping these liquid crystal panels with external peripheral driversand a backlight unit. The performance of the TFTs themselves washigh-quality, and since the manufacturing process is also reliable, itwas possible to manufacture liquid crystal display devices having highdisplay quality at low cost. In addition, the performance of TFTs wasextremely high, and since the necessary driver circuits can be formed onthe active matrix substrate (integrated drivers), it was possible tosimplify the packaging configuration with the outside peripheral drivercircuits and achieve a compact, lightweight liquid crystal displaydevice.

[0136] These types of liquid crystal display devices were installed inthe case of a full-color notebook PC, thus achieving at low cost themanufacture of a compact, lightweight full-color notebook PC having gooddisplay quality.

Possible Industrial Applications

[0137] As stated above, the method of fabricating thin filmsemiconductor devices described by this invention enables themanufacture of high performance thin film semiconductor devices using alow temperature process in which inexpensive glass substrates can beused. Therefore, applying this invention to the manufacture of activematrix liquid crystal display devices permits large-size, high-qualityliquid crystal display devices to be manufactured easily and reliably.Moreover, when this invention is applied to the manufacture of otherelectronic circuits, high-quality electronic circuits can also bemanufactured easily and reliably. Additionally, since the thin filmsemiconductor device of this invention is both low-cost andhigh-performance, it is optimum for active matrix substrates for activematrix liquid crystal displays. it is especially well-suited forintegrated driver active matrix substrates, which require highperformance.

[0138] Additionally, since the liquid crystal displays of this inventionare low-cost and high-performance, they are optimum for full-colornotebook PCs and all types of displays.

[0139] Additionally, since the electronic circuits of this invention arelow-cost and high-performance, they will likely find wide acceptance.

1. A thin film semiconductor device, comprising a substrate upon atleast a portion of which is formed an underlevel protection layer of aninsulating material; and a semiconductor film, serving as the activelayer of a transistor, formed upon said underlevel protection layer ofthe substrate; a thin film semiconductor device having a center linemean roughness value for the surface roughness of the aforementionedunderlevel protection layer of about 3.0 nm or less.
 2. A thin filmsemiconductor device as described in claim 1 above having a center linemean roughness value for the surface roughness of the aforementionedunderlevel protection layer of about 1.5 nm or less.
 3. A fabricationprocess of a thin film semiconductor device comprising the formation ofan underlevel protection layer of an insulating material upon at least aportion of a substrate; and further the formation of a semiconductorfilm, which is the active layer of a transistor, upon said underlevelprotection layer; a thin film semiconductor device fabrication processcomprising two steps in which step one is the formation of asemiconductor film upon an underlevel protection layer having a centerline mean roughness value for the surface roughness of about 1.5 nm orless and step two is the melt crystallization of said semiconductorfilm.
 4. A thin film semiconductor device comprising a substrate upon atleast a portion of which is formed an underlevel protection layer of aninsulating material; and a semiconductor film, serving as the activelayer of a transistor, formed upon said underlevel protection layer ofthe substrate; a thin film semiconductor device having theaforementioned underlevel protection layer comprising at least twodifferent deposited films in which the film comprising the upper mostlayer of the aforementioned two different types of films is a siliconoxide film (SiO_(x), O<×≦2).
 5. A thin film semiconductor device asdescribed in claim 4 above in which the film comprising the bottom mostlayer of the aforementioned two different types of films is a siliconnitride film (Si₃N_(x), O<×≦4).
 6. A thin film semiconductor device asdescribed in claim 5 above in which the thickness of the aforementionedsilicon oxide layer is between about 100 nm and 500 nm, and thethickness of the aforementioned silicon nitride layer is between about100 nm and 500 nm.
 7. A thin film semiconductor device comprising asubstrate upon at least a portion of which is formed an underlevelprotection layer of an insulating material; and a field effecttransistor having a semiconductor film formed upon said underlevelprotection layer of the substrate, a gate insulator layer, and a gateelectrode; and an electrically insulating interlevel insulator layerbetween the interconnects of said field effect: transistor; a thin filmsemiconductor device having a sum of the thicknesses of theaforementioned underlevel protection layer, the aforementioned gateinsulator layer, and the aforementioned interlevel insulator layer ofabout 2 mm or less.
 8. A fabrication process of a thin filmsemiconductor device comprising the formation of an underlevelprotection layer of an insulating material upon at least a portion of asubstrate; and further the formation of a semiconductor film, which isthe active layer of a transistor, upon said underlevel protection layer;a thin film semiconductor device fabrication process comprising a filmfabrication process involving the sequential formation of saidunderlevel protection layer and said semiconductor film using a singlePECVD reactor with the following six step procedure: the removal offilms adhered in the deposition chamber of said PECVD reactor in stepone, the formation of a passivation layer in said deposition chamber instep 2, the setting of substrate(s) in said deposition chamber in step3, the formation of an underlevel protection layer upon saidsubstrate(s) in step 4, the formation of a semiconductor layer upon saidunderlevel protection layer in step 5, the removal of said substrate(s)from said deposition chamber in step
 6. 9. A fabrication process of athin film semiconductor device comprising the formation of an underlevelprotection layer of an insulating material upon at least a portion ofabout a 90000 mm² or larger surface area (S) substrate; and further theformation of a semiconductor film, which is the active layer of atransistor, upon said underlevel protection layer; a thin filmsemiconductor device fabrication process comprising the formation of thesemiconductor film under conditions satisfying the relationshipd>0.02XS^(1/2) when setting multiple substrates in the depositionchamber of an LPCVD reactor at a substrate spacing d (mm) and formingsaid semiconductor film by the LPCVD method.
 10. A fabrication processof a thin film semiconductor device comprising the formation of anunderlevel protection layer of an insulating material upon at least aportion of a substrate; and further the formation of asilicon-containing semiconductor film, which is the active layer of atransistor, upon said underlevel protection layer; a thin filmsemiconductor device fabrication process comprising the formation of thesemiconductor film under conditions in which the LPCVD method using ahigher silane (Si_(n)H_(2n×2): n is an integer greater than or equal to2) as a source gas is used to form said semiconductor film, and thehigher silane flow rate per unit area (R) is about 1.13×10 ⁻³ sccm/cm²or more.
 11. A thin film semiconductor device fabrication process asdescribed in claim 10 above in which the semiconductor film is formedunder the conditions of R greater than or equal to about 2.27×10⁻³sccm/cm².
 12. A fabrication process of a thin film semiconductor devicecomprising the formation of an underlevel protection layer of aninsulating material upon at least a portion of a substrate; and furtherthe formation of a silicon-containing semiconductor film, which is theactive layer of a transistor, upon said underlevel protection layer; athin film semiconductor device fabrication process comprising theformation of the semiconductor film under conditions in which the LPCVDmethod with a higher silane (Si_(n)H_(2n+2): n is an integer greaterthan or equal to 2) as a least one type of source gas and a depositiontemperature less than about 450° C. is used to form the aforementionedsemiconductor film with a deposition rate (DR) of about 0.20 nm/min ormore.
 13. A thin film fabrication process as described in claim 12 abovein which the semiconductor film is formed with a deposition rate ofabout 0.60 nm/min or more.
 14. A thin film semiconductor devicecomprising a substrate upon at least a portion of which is formed anunderlevel protection layer of an insulating material; and asemiconductor film, serving as the active layer of a transistor, formedupon said-underlevel protection layer of the substrate; a thin filmsemiconductor device comprising a semiconductor film formed by LPCVD ata deposition temperature of less than about 450° C. followed bycrystallization and having a film thickness between about 10 nm and 140nm, inclusive.
 15. A fabrication process of a thin film semiconductordevice in which a semiconductor film is formed on the surface of a glasssubstrate and said semiconductor film is the active layer of atransistor, a thin film semiconductor fabrication process comprising theuse of a hot wall, vertical LPCVD reactor to form the aforementionedsemiconductor film, and, in so doing, making pairs of two substrates,from multiple glass substrates comprising two or more types withdifferent strain points, by combining them back to back and placing themapproximately parallel within the hot wall, vertical reactor, andplacing the higher strain point glass substrate on the bottom of saidtwo-substrate pairs for the semiconductor film deposition step.
 16. Afabrication process of a thin film semiconductor device comprising theformation of an underlevel protection layer of an insulating materialupon a portion of a substrate; and further the formation of asemiconductor film, which is the active layer of a transistor, upon saidunderlevel protection layer; a thin film semiconductor devicefabrication process comprising the use of a PECVD reactor for formationof the aforementioned semiconductor film, and, in so doing, using aformation procedure comprising the exposure of the underlevel protectionlayer to an oxygen plasma as the first step and sequentially forming thesemiconductor film on top of said underlevel protection layer withoutbreaking vacuum as the second step.
 17. A thin film semiconductor devicefabrication process as described in claim 16 above in which vacuum ispulled in the deposition chamber between steps one and two.
 18. In thefabrication process of a thin film semiconductor device comprising theformation of an underlevel protection layer of an insulating materialupon at least a portion of a substrate; and further the formation of asemiconductor film, which is the active layer of a transistor, upon saidunderlevel protection layer; a thin film semiconductor devicefabrication process comprising the use of a PECVD reactor for formationof the aforementioned semiconductor film, and, in so doing, using aformation procedure comprising the exposure of the underlevel protectionlayer to a hydrogen plasma as the first step and sequentially formingthe semiconductor film on top of said underlevel protection layerwithout breaking vacuum as the second step.
 19. A fabrication process ofa thin film semiconductor device comprising the formation of anunderlevel protection layer of an insulating material upon at least aportion of a substrate; and further the formation of a semiconductorfilm, which is the active layer of a transistor, upon said underlevelprotection layer; a thin film semiconductor device fabrication processcomprising the use of a PECVD reactor for formation of theaforementioned semiconductor film, and, in so doing, using a formationprocedure comprising the exposure of the underlevel protection layer toan oxygen plasma as the first step, sequential exposure of theunderlevel protection layer to a hydrogen plasma without breaking vacuumas the second step, and sequential formation of the semiconductor filmon top of said underlevel protection layer as the third step.
 20. A thinfilm semiconductor device fabrication process as described in claim 19above in which vacuum is pulled in the deposition chamber between stepsone and two.
 21. A fabrication process of a thin film semiconductordevice comprising the formation of an underlevel protection layer of aninsulating material upon a portion of a substrate; and further theformation of a semiconductor film, which is the active layer of atransistor, upon said underlevel protection layer; a thin filmsemiconductor device fabrication process comprising the use of a PECVDreactor for formation of the aforementioned semiconductor film, and, inso doing, using a formation procedure comprising the formation of thesemiconductor film on top of said underlevel protection layer as thefirst step, and the sequential exposure of said semiconductor film to ahydrogen plasma without breaking vacuum as the second step.
 22. Afabrication process of a thin film semiconductor device comprising theformation of an underlevel protection layer of an insulating materialupon at least a portion of a substrate; and further the formation of asemiconductor film, which is the active layer of a transistor, upon saidunderlevel protection layer; a thin film semiconductor devicefabrication process comprising the use of a PECVD reactor for formationof the aforementioned semiconductor film, and, in so doing, using aformation procedure comprising the formation of the semiconductor filmon top of said underlevel protection layer as the first step, and thesequential exposure of said semiconductor film to an oxygen plasmawithout breaking vacuum as the second step.
 23. A fabrication process ofa thin film semiconductor device comprising the formation of anunderlevel protection layer of an insulating material upon at least aportion of a substrate; and further the formation of a semiconductorfilm, which is the active layer of a transistor, upon said underlevelprotection layer; a thin film semiconductor device fabrication processcomprising the use of a PECVD reactor for formation of theaforementioned semiconductor film, and, in so doing, using a formationprocedure comprising the formation of the semiconductor film on top ofsaid underlevel protection layer as the first step, the sequentialexposure of said semiconductor film to a hydrogen plasma withoutbreaking vacuum as the second step, and the further sequential exposureof said semiconductor film to an oxygen plasma without breaking vacuumas the third step.
 24. A fabrication process of a thin filmsemiconductor device comprising the formation of an underlevelprotection layer of an insulating material upon at least a portion of asubstrate; and further the formation of a semiconductor film, which isthe active layer of a transistor, upon said underlevel protection layer;a thin film semiconductor device fabrication process comprising theformation of a semiconductor film on top of the underlevel protectionlayer as the first step, the removal of an oxide layer from the surfaceof said semiconductor film as the second step, and melt crystallizationimmediately after the removal of the oxide layer as the third step. 25.A fabrication process of a thin film semiconductor device comprising theformation of an underlevel protection layer of an insulating materialupon at least a portion of a substrate; and further the formation of asemiconductor film, which is the active layer of a transistor, upon saidunderlevel protection layer; a thin film semiconductor devicefabrication process comprising the use of PECVD with a deposition rateof approximately 0.1 nm/s or more to form a mixed-crystallinitysemiconductor film as the first step, and the melt crystallization ofsaid semiconductor film as the second step.
 26. A thin filmsemiconductor device fabrication process as described in claim 25 abovein which the deposition rate in the first step is approximately 3.7 nm/sor more to form the mixed amorphous-crystalline semiconductor film. 27.A fabrication process of a thin film semiconductor device comprising theformation of an underlevel protection layer of an insulating materialupon at least a portion of a substrate; and.further the formation of asemiconductor film, which is the active layer of a transistor, upon saidunderlevel protection layer; a thin film semiconductor devicefabrication process comprising use of PECVD, in which chemical speciescontaining the constitutive elements of said semiconductor film andinert gases are used as source gases with the ratio of the flow rate ofthe gas containing the constitutive elements of the semiconductor filmto the flow rate of the inert gas less than about 1/33, to form amixed-crystallinity semiconductor film as the first step, and the meltcrystallization of said semiconductor film as the second step.
 28. Athin film semiconductor device fabrication process as described in claim27 above in which the aforementioned gas flow ratio in theaforementioned step 1 is between about 1/124 and 40.67/1 for thedeposition of a mixed-crystallinity semiconductor film using PECVD. 29.A thin film semiconductor device comprising a substrate upon at least aportion of which is formed an underlevel protection layer of aninsulating material; and a semiconductor film, serving as the activelayer of a transistor, formed upon said underlevel protection layer ofthe substrate: a thin film semiconductor device comprising the formationof said semiconductor film by PECVD growth followed by crystallizationin which the thickness of the semiconductor film is between about 9 nmand 135 nm, inclusive.
 30. A fabrication process of a thin filmsemiconductor device comprising the formation of a semiconductor filmupon an insulating material which is at least a portion of the surfaceof a substrate; and said semiconductor film acting as the active layerof a transistor; a thin film semiconductor device fabrication processcomprising the use of low pressure chemical vapor deposition (LPCVD) todeposit the semiconductor film at a deposition temperature less thanabout 450° C. as step one, the irradiation of said semiconductor film byoptical or electromagnetic energy as step two, and further, a maximumprocessing temperature of about 350° C. or less following the completionof said step two.
 31. A thin film semiconductor device fabricationprocess as described in claim 30 above in which the depositiontemperature of the semiconductor film is about 430° C. or less.
 32. Afabrication process of a thin film semiconductor device comprising theformation of a semiconductor film upon an insulating material which isat least a portion of the surface of a substrate; and said semiconductorfilm acting as the active layer of a transistor; a thin filmsemiconductor device fabrication process comprising the formation of thesemiconductor film at a deposition temperature of about 350° C. or less,the irradiation of said semiconductor film by optical or electromagneticenergy as step two, and further, a maximum processing temperature ofabout 350° C. or less following the completion of said step two.
 33. Athin film semiconductor device fabrication process as described in claim32 above in which step one is carried out by plasma enhanced chemicalvapor deposition (PECVD).
 34. A thin film semiconductor devicefabrication process as described in claim 32 above in which step one iscarried out by sputtering.
 35. A fabrication process of a thin filmsemiconductor device comprising the formation of a semiconductor filmupon an insulating material which is at least a portion of the surfaceof a substrate; and said semiconductor film acting as the active layerof a transistor; a thin film semiconductor device fabrication processcomprising the fabrication of the semiconductor film by VHF plasmaenhanced chemical vapor deposition (VHF-PECVD) as step one, and furthera maximum processing temperature of about 350° C. or less following thecompletion of said step one.
 36. A thin film semiconductor devicefabrication process as described in claim 35 above in which thethickness of said semiconductor film formed in the aforementioned stepone is between about 20 nm and 150 nm.
 37. A thin film semiconductordevice fabrication process as described in claim 35 or claim 36 above inwhich, during the formation of the semiconductor film in theaforementioned step one, a chemical specie containing the constitutiveelements of said semiconductor film is used as a source gas, and,further, a noble gas is used as a dilution gas.
 38. A thin filmsemiconductor device fabrication process as described in claim 37 abovein which the chemical specie containing the constitutive elements of theaforementioned semiconductor film is a silane (SiH₄, Si₂H₆, Si₃H₈). 39.A thin film semiconductor device fabrication process as described inclaim 37 or claim 38 above in which the aforementioned noble gas ishelium (He).
 40. A thin film semiconductor device fabrication process asdescribed in claim 37 or claim 38 above in which the aforementionednoble gas is neon (Ne).
 41. A thin film semiconductor device fabricationprocess as described in claim 37 or claim 38 above in which theaforementioned noble gas is argon (Ar).
 42. A fabrication process of athin film semiconductor device comprising the formation of a crystallinesemiconductor film upon an insulating material which is at least aportion of the surface of a substrate; and said crystallinesemiconductor film acting as the active layer of a transistor; a thinfilm semiconductor device fabrication process comprising the fabricationof the crystalline semiconductor film by microwave plasma enhancedchemical vapor deposition (microwave-PECVD) as step one, and further, amaximum processing temperature of about 350° C. or less after said stepone.
 43. A thin film semiconductor device fabrication process asdescribed in claim 42 above in which, during the formation of thecrystalline semiconductor film by means of those in the aforementionedstep one, the film thickness of said crystalline semiconductor film isbetween about 20 and 150 nm.
 44. A thin film semiconductor devicefabrication process as described in claim 42 or claim 43 above in which,during the formation of the crystalline semiconductor film in theaforementioned step one, a chemical specie containing the constitutiveelements of said crystalline semiconductor film is used as a source gas,and, further, a noble gas is used as a dilution gas.
 45. A thin filmsemiconductor device fabrication process as described in claim 44 abovein which the chemical specie containing the constitutive elements of theaforementioned crystalline semiconductor film is a silane (SiH₄, Si₂H₆,Si₃H₈).
 46. A thin film semiconductor device fabrication process asdescribed in claim 44 or claim 45 above in which the aforementionednoble gas is helium (He).
 47. A thin film semiconductor devicefabrication process as described in claim 44 or claim 45 above in whichthe aforementioned noble gas is neon (Ne).
 48. A thin film semiconductordevice fabrication process as described in claim 44 or claim 45 above inwhich the aforementioned noble gas is argon (Ar).
 49. A fabricationprocess of a thin film semiconductor device comprising the formation ofa semiconductor film upon an insulating material which is at least aportion of the surface of a substrate; and said semiconductor filmacting as the active layer of a transistor; a thin film semiconductordevice fabrication process comprising the fabrication of thesemiconductor film by VHF plasma enhanced chemical vapor deposition(VHF-PECVD) as step one, the crystallization of said semiconductor filmas step two, and further, a maximum processing temperature of about 350°C. or less after said step two.
 50. A thin film semiconductor devicefabrication process as described in claim 49 above in which the filmthickness of the semiconductor film crystallized in the aforementionedstep two is between about 10 and 150 nm.
 51. A thin film semiconductordevice fabrication process as described in claim 49 or claim 50 above inwhich, during the formation of the crystalline semiconductor film in theaforementioned step one, a chemical specie containing the constitutiveelements of said crystalline semiconductor film is used as a source gas,and, further, a noble gas is used as a dilution gas.
 52. A thin filmsemiconductor device fabrication process as described in claim 51 abovein which the chemical specie containing the constitutive elements of theaforementioned crystalline semiconductor film is a silane (SiH₄, Si₂H₆,Si₃H₈).
 53. A thin film semiconductor device fabrication process asdescribed in claim 51 or claim 52 above in which the aforementionednoble gas is helium (He).
 54. A thin film semiconductor devicefabrication process as described in claim 51 or claim 52 above in whichthe aforementioned noble-gas is neon (Ne).
 55. A thin film semiconductordevice fabrication process as described in claim 51 or claim 52 above inwhich the aforementioned noble gas is argon (Ar).
 56. A fabricationprocess of a thin film semiconductor device comprising the formation ofa crystalline semiconductor film upon an insulating material which is atleast a portion of the surface of a substrate; and said crystallinesemiconductor film acting as the active layer of a transistor; a thinfilm semiconductor device fabrication process comprising the fabricationof the semiconductor film by microwave plasma enhanced chemical vapordeposition (microwave-PECVD) as step one, crystallization of saidsemiconductor film as step two, and further, a maximum processingtemperature of about 350° C. or less after said step two.
 57. A thinfilm semiconductor device fabrication process as described in claim 56above in which the film thickness of the semiconductor film crystallizedby means of the aforementioned step two is between about 10 and 150 nm.58. A thin film semiconductor device fabrication process as described inclaim 56 or claim 57 above in which, during the formation of thecrystalline semiconductor film in the aforementioned step one, achemical specie containing the constitutive elements of said crystallinesemiconductor film is used as a source gas, and, further, a noble gas isused as a dilution gas.
 59. A thin film semiconductor device fabricationprocess as described in claim 58 above in which the chemical speciecontaining the constitutive elements of the aforementioned crystallinesemiconductor film is a silane (SiH₄, Si₂H₆, Si₃H₈).
 60. A thin filmsemiconductor device fabrication process as described in claim 58 orclaim 59 above in which the aforementioned noble gas is helium (He). 61.A thin film semiconductor device fabrication process as described inclaim 58 or claim 59 above in which the aforementioned noble gas is neon(Ne).
 62. A thin film semiconductor device fabrication process asdescribed in claim 58 or claim 59 above in which the aforementionednoble gas is argon (Ar).
 63. A liquid crystal display characterized bythe use of a thin film semiconductor device as described in any one ofclaim 1 , claim 2 , claim 4 , claim 5 , claim 6 , claim 7 , claim 14 ,and claim 29 .
 64. An electronic device characterized by theincorporation of a liquid crystal display as described in claim 63above.